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公开(公告)号：US20220173739A1
公开(公告)日：2022-06-02
申请号：US17515233
申请日：2021-10-29
Inventor： Xiangye WEI , Liming XIU
Abstract: An integrated circuit is provided. The integrated circuit includes: a clock source configured to: generate a clock signal of the integrated circuit; at least two functional circuits; and at least two clock generators corresponding to the functional circuits and configured to: determine initial phases of the corresponding functional circuits, and generate clock signals of the functional circuits based on the clock signal of the integrated circuit and the initial phases, so as to keep the clock signals of all the functional circuits synchronized, wherein the initial phases are determined based on transmission distances, over which the clock signal of the integrated circuit is transmitted from the clock source to the functional circuits, and loads of the functional circuits.
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12.发明申请公开(公告)号：US20190261472A1
公开(公告)日：2019-08-22
申请号：US16080827
申请日：2017-12-15
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Liming XIU
Abstract: A signal generating circuit and a signal generating method, a driving circuit of a light emitting device and a display device. The signal generating circuit includes: a control circuit, configured to calculate at least one of frequency control word information (or duty-cycle control word information according to an instruction; and a pulse-width adjusting circuit, configured to generate a pulse signal according to the at least one of the frequency control word information or the duty-cycle control word information.
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13.发明公开公开(公告)号：US20240089003A1
公开(公告)日：2024-03-14
申请号：US17767763
申请日：2021-03-09
Inventor： Xiangye WEI , Liming XIU , Yiming BAI , Xin LI
IPC: H04B10/50
CPC classification number: H04B10/502
Abstract: An optical communication device, an optical communication system, and a method for establishing a communication connection are provided, relating to communications technology. In the optical communication device, the first driving circuit can control, based on the generated first target plaintext, the optical signal transmitting circuit to transmit the first optical signal, and control, based on the generated first key, the optical signal transmitting circuit to transmit the second optical signal. That is, an optical communication device that detects the optical signals can establish, based on the optical signals, a communication connection with the optical communication device that transmits the optical signals.
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公开(公告)号：US20240078201A1
公开(公告)日：2024-03-07
申请号：US18271865
申请日：2022-07-01
Inventor： Xiangye WEI , Liming XIU
CPC classification number: G06F13/1689 , G06F5/10 , G06F13/1621
Abstract: Provide is a FIFO memory system. The FIFO memory system includes: a FIFO memory; a read clock frequency circuit, configured to provide at least two clock signals, wherein the at least two clock signals include a first clock signal and a second clock signal, a frequency of the first clock signal being greater than a frequency of the second clock signal; and a controller, configured to determine a data volume in the FIFO memory, control the read clock frequency circuit to output the first clock signal in a case that the data volume in the FIFO memory is in a first range, or control the read clock frequency circuit to output the second clock signal in a case that the data volume in the FIFO memory is in a second range, the lower limit of the first range being not less than an upper limit of the second range.
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公开(公告)号：US20230403166A1
公开(公告)日：2023-12-14
申请号：US18033807
申请日：2020-10-28
Inventor： Xiangye WEI , Liming XIU
IPC: H04L9/32
CPC classification number: H04L9/3278 , H04L9/3236
Abstract: A data processing method, including: obtaining a challenge sequence of challenge-response pairs, and generating, by a physical unclonable function, an original response sequence corresponding to the challenge-response pairs; generating a first index parameter according to the challenge sequence, and obtaining feature bit information in the original response sequence according to the first index parameter; converting the challenge sequence to generate a second index parameter, and updating the first index parameter according to the second index parameter and the feature bit information; obtaining new feature bit information in the original response sequence according to the updated first index parameter; and repeatedly generating second index parameters, updating the first index parameter according to the second index parameters and the latest obtained feature bit information, and obtaining multiple pieces of feature bit information, to generate a target response sequence according to the multiple pieces of feature bit information.
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Patent Agency Ranking
公开(公告)号：US20230176820A1
公开(公告)日：2023-06-08
申请号：US17778581
申请日：2021-07-07
Inventor： Xiangye WEI , Liming XIU
IPC: G06F7/58
CPC classification number: G06F7/588
Abstract: Provided is a random number generator . The random number generator includes: a control word providing circuit, a pulse generating circuit and a random number generating circuit. The control word providing circuit is configured to generate a plurality of control words in response to a first rule. The pulse generating circuit is connected to the control word providing circuit and configured to output a plurality of channels of pulse signals in response to the plurality of control words, The random number generating circuit is connected to the pulse generating circuit and configured to generate a random number sequence by performing a logical operation on the plurality of pulse signals .
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17.发明申请公开(公告)号：US20220407507A1
公开(公告)日：2022-12-22
申请号：US17765933
申请日：2021-03-09
Inventor： Xiangye WEI , Liming XIU
Abstract: A clock signal generation circuit and method, and an electronic device are provided, relating to the field of communications technology. In the clock signal generation circuit, an initial clock providing circuit (10) can generate an initial clock signal having an initial frequency; a control word providing circuit (20) can determine a target frequency offset of the initial frequency based on a detected target parameter and generate a frequency control word based on the target frequency offset; a target clock generating circuit (30) can generate a target clock signal having a target output frequency based on the frequency control word and the initial clock signal, wherein the target output frequency is negatively correlated with the frequency control word and positively correlated with the initial frequency. It can be learned based on a relationship among the target output frequency and the initial frequency and the frequency control word that flexibly generating the frequency control word can reduce the impact of the target parameter on the frequency of the clock signal finally generated by the clock signal generation circuit.
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公开(公告)号：US20220131684A1
公开(公告)日：2022-04-28
申请号：US17333110
申请日：2021-05-28
Inventor： Xiangye WEI , Liming XIU
Abstract: The present disclosure provides a hash algorithm circuit, a hash algorithm method, and an electronic device. The hash algorithm circuit is used to reduce fixed-length parallel data, and the reduced identifier can be used as an index reference, an identifier ID, an address extension bit, information summary, and so on. The hash algorithm circuit has the characteristics of low power consumption, low cost, etc., and can be integrated in a digital circuit.
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公开(公告)号：US20210224035A1
公开(公告)日：2021-07-22
申请号：US16099479
申请日：2018-01-05
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Liming XIU
IPC: G06F7/509
Abstract: The present disclosure relates to aft XIU-accumulating register, aft XIU-accumulating register circuit, and an electronic device. The XIU-accumulating register includes a first accumulating unit and a second accumulating unit. The first accumulating unit includes a first adder and a first register; the first adder is configured to accumulate fractional bit data of an accumulated variable, and the first register is configured to store an accumulated result of the fractional bit data and carry bit data of the accumulated result of the fractional bit data. The second accumulating unit includes a second adder and a second register; the second adder is configured to accumulate integer bit data of the accumulated variable, and the second register is configured to store an accumulated result of the integer bit data.
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公开(公告)号：US20190238143A1
公开(公告)日：2019-08-01
申请号：US16215857
申请日：2018-12-11
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Liming XIU
Abstract: An electronic device includes: an acquisition circuit, configured to collect the current environmental information for characterizing the environment of the electronic device; a processing circuit, configured to receive the current environmental information from the acquisition circuit; determine a target frequency control word corresponding to the current environmental information according to a preset expected operating status of the electronic device; and input the target frequency control word to the TAF-DPS clock generator; the TAF-DPS clock generator, configured to generate a clock signal according to the target frequency control word, and output the clock signal to a functional circuit; the functional circuit, configured to operate in accordance with the clock signal to make the electronic device reach the expected operating status.
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