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    Neural Network Architecture
    11.
    发明申请
    Neural Network Architecture 有权

    公开(公告)号：US20210365764A1

    公开(公告)日：2021-11-25

    申请号：US16879587

    申请日：2020-05-20

    Applicant: Arm Limited

    Inventor： Mbou Eyole ,  Shidhartha Das ,  Femando Garcia Redondo

    IPC: G06N3/063 ,  G06N3/04

    Abstract: Various implementations are related to an apparatus with memory cells arranged in columns and rows, and the memory cells are accessible with a column control voltage for accessing the memory cells via the columns and a row control voltage for accessing the memory cells via the rows. The apparatus may include neural network circuitry having neuronal junctions that are configured to receive, record, and provide information related to incoming voltage spikes associated with input signals based on resistance through the neuronal junctions. The apparatus may include stochastic re-programmer circuitry that receives the incoming voltage spikes, receives the information provided by the neuronal junctions, and reconfigure the information recorded in the neuronal junctions based on the incoming voltage spikes associated with the input signals along with a programming control signal provided by the memory circuitry.

    Online instruction tagging
    12.
    发明授权
    Online instruction tagging 有权

    公开(公告)号：US11163581B2

    公开(公告)日：2021-11-02

    申请号：US16658490

    申请日：2019-10-21

    Applicant: Arm Limited

    Inventor： Mbou Eyole ,  Michiel Willem Van Tol

    IPC: G06F9/38 ,  G06F9/30

    Abstract: Apparatuses and methods of data processing are disclosed for tagging instructions on-line. Instruction tag storage stores information indicative of a tag applied to certain instruction identifiers. A data processing operation performed by the data processing circuitry in response to an executed instruction is dependent on whether there is a corresponding instruction identifier for the executed instruction in the instruction tag storage which has the instruction tag. Register writer storage is maintained, and an entry is created for each register writing instruction encountered which causes a result value to be written to a destination register, where the entry comprises an indication of the destination register and the register writing instruction. An instruction tagging queue buffers instruction identifiers and an instruction identifier is added to the queue for a predetermined type of instruction when it is encountered. Instruction tagging circuitry tags the instructions in the instruction tagging queue and determines one or more producer instructions which each produce at least one data value which is a source operand of a subject instruction and adds the one or more producer instructions to the instruction tagging queue. Data dependency graphs are thus elaborated and online tagging of such data dependency graphs is thus supported.

    Reconfigurable Circuit Architecture
    13.
    发明申请
    Reconfigurable Circuit Architecture 审中-公开

    公开(公告)号：US20200226095A1

    公开(公告)日：2020-07-16

    申请号：US16645993

    申请日：2018-09-25

    Applicant: Arm Limited

    Inventor： Mbou Eyole ,  Emre Ozer ,  Xabier Iturbe ,  Shidhartha Das

    IPC: G06F15/78 ,  G11C14/00 ,  H03K19/17728

    Abstract: A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.

    TECHNIQUES FOR CONTROLLING VECTOR PROCESSING OPERATIONS
    14.
    发明申请
    TECHNIQUES FOR CONTROLLING VECTOR PROCESSING OPERATIONS 有权

    公开(公告)号：US20250028530A1

    公开(公告)日：2025-01-23

    申请号：US18711220

    申请日：2022-10-18

    Applicant: Arm Limited

    Inventor： Mbou Eyole ,  Michael Alexander Kennedy ,  Giacomo Gabrielli

    IPC: G06F9/30 ,  G06F15/82

    Abstract: There is provided a processing apparatus comprising decoder circuitry. The decoder circuitry is configured to generate control signals in response to an instruction. The processing apparatus further comprises processing circuitry which comprising a plurality of processing lanes. The processing circuitry is configured, in response to the control signals, to perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing for that processing lane is enabled. The processing apparatus further comprises control circuitry to monitor each processing lane of the plurality of processing lanes for each instruction of a plurality of instructions performed in the plurality of processing lanes and to modify the per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane meeting one or more predetermined conditions.

    Post-manufacturing adaptation of a data processing apparatus
    15.
    发明授权
    Post-manufacturing adaptation of a data processing apparatus 有权

    公开(公告)号：US12093121B2

    公开(公告)日：2024-09-17

    申请号：US17547963

    申请日：2021-12-10

    Applicant: Arm Limited

    Inventor： Emre Ozer ,  Mbou Eyole ,  Jedrzej Kufel ,  John Philip Biggs

    IPC: G06F11/07 ,  G06F13/24 ,  G06F30/20

    CPC classification number: G06F11/0787 ,  G06F13/24 ,  G06F30/20

    Abstract: Methods of performing post-manufacturing adaptation of a data processing apparatus manufactured in accordance with a processor design and corresponding data processing apparatus configurations are provided. Post-manufacturing testing of the data processing apparatus determines any dysfunctional instructions by comparison between component usage profiles for each instruction and a component fault-detection procedure applied to the data processing apparatus. The data processing apparatus can be determined nevertheless to be operationally viable when any dysfunctional instructions can be substituted for by emulation using other functional instructions. The data processing apparatus can be provided with dysfunctional instruction handling circuitry configured to identify occurrence of a program instruction instance of a dysfunctional instruction and to invoke an interrupt handling routine associated with the dysfunctional instruction to emulate the instance of a dysfunctional instruction.

    BRAIN-COMPUTER INTERFACE DEVICE, SYSTEM AND OPERATING METHOD
    16.
    发明公开
    BRAIN-COMPUTER INTERFACE DEVICE, SYSTEM AND OPERATING METHOD 审中-公开

    公开(公告)号：US20240193251A1

    公开(公告)日：2024-06-13

    申请号：US18063597

    申请日：2022-12-08

    Applicant: Arm Limited

    Inventor： Remy Pottier ,  Hugo John Martin Vincent ,  Mbou Eyole ,  Michael James Kanellos

    IPC: G06F21/44 ,  G06F3/01

    CPC classification number: G06F21/44 ,  G06F3/015

    Abstract: A method and apparatus to control operation of a brain-computer interface, comprising: capturing, at a sensor, a time series of brain activity in response to stimuli; passing data for the time series of brain activity to a history-based challenge generator; receiving, from the history-based challenge generator, a challenge comprising a generated stimulus with a predicted brain response derived from data for the time series of brain activity; issuing the challenge over the brain-computer interface; capturing, at the sensor, a brain response to the challenge; comparing, by an authenticator, the brain response to the challenge with the predicted brain response for the generated stimulus; and responsive to finding no match between the brain response to the challenge and the predicted brain response, preventing further activity over the brain-computer interface.

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