Abstract:
Embodiments of a local interface unit are disclosed that may allow for managing credits and tokens as part of flow control method. The local interface unit may include a transmit unit and a receive unit. The transmit unit may be configured to receive credits and tokens, determine an available number of credits based on the number received tokens, determine an available number of tokens based on the number of received tokens, and send the available credits to an arbitration unit. The available credits may then be updated, by the transmit unit in response to receiving a selected transaction from the arbitration, and the transmit unit may then transmit the selected transaction, and update the available credits and the available tokens once the transaction has been sent. The receive unit may be configured to send credits and tokens to a transmit unit, and receive a transaction sent by a transmit unit.
Abstract:
Systems and methods for upgrading QoS levels of older transactions based on the presence of higher level QoS transactions in a given queue. A counter may be maintained to track the number of transactions in a queue that are assigned a corresponding QoS level. Each separate QoS level can have a corresponding counter. When a transaction is received by the queue, the counter corresponding to the QoS level of the transaction is incremented. When a transaction leaves the queue, the transaction is upgraded to the highest QoS level with a non-zero counter. Also, when the transaction leaves the queue, the counter corresponding to the original QoS level of the transaction is decremented.
Abstract:
Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.
Abstract:
A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.