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    Non-shifting reservation station
    11.
    发明授权
    Non-shifting reservation station 有权

    公开(公告)号：US10678542B2

    公开(公告)日：2020-06-09

    申请号：US14808811

    申请日：2015-07-24

    Applicant: Apple Inc.

    Inventor： Ian D. Kountanis ,  Mahesh K. Reddy

    IPC: G06F9/30

    Abstract: Systems, apparatuses, and methods for implementing a non-shifting reservation station. A dispatch unit may write an operation into any entry of a reservation station. The reservation station may include an age matrix for determining the relative ages of the operations stored in the entries of the reservation station. The reservation station may include selection logic which is configured to pick the oldest ready operation from the reservation station based on the values stored in the age matrix. The selection logic may utilize control logic to mask off columns of an age matrix corresponding to non-ready operation so as to determine which operation is the oldest ready operation in the reservation station. Also, the reservation station may be configured to dequeue operations early when these operations do not have load dependency.

    Cache for patterns of instructions with multiple forward control transfers
    13.
    发明授权
    Cache for patterns of instructions with multiple forward control transfers 有权

    公开(公告)号：US09632791B2

    公开(公告)日：2017-04-25

    申请号：US14160242

    申请日：2014-01-21

    Applicant: Apple Inc.

    Inventor： Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Ronald P. Hall ,  Michael L. Karm

    IPC: G06F12/08 ,  G06F9/38 ,  G06F12/0862

    CPC classification number: G06F9/3844 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3867 ,  G06F12/0862 ,  Y02D10/13

    Abstract: Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.

    NON-SHIFTING RESERVATION STATION
    14.
    发明申请
    NON-SHIFTING RESERVATION STATION 审中-公开
    非转移预留站

    公开(公告)号：US20170024205A1

    公开(公告)日：2017-01-26

    申请号：US14808811

    申请日：2015-07-24

    Applicant: Apple Inc.

    Inventor： Ian D. Kountanis ,  Mahesh K. Reddy

    IPC: G06F9/30

    Abstract: Systems, apparatuses, and methods for implementing a non-shifting reservation station. A dispatch unit may write an operation into any entry of a reservation station. The reservation station may include an age matrix for determining the relative ages of the operations stored in the entries of the reservation station. The reservation station may include selection logic which is configured to pick the oldest ready operation from the reservation station based on the values stored in the age matrix. The selection logic may utilize control logic to mask off columns of an age matrix corresponding to non-ready operation so as to determine which operation is the oldest ready operation in the reservation station. Also, the reservation station may be configured to dequeue operations early when these operations do not have load dependency.

    Abstract translation: 用于实施非移动保留站的系统，装置和方法。 调度单元可以将操作写入保留站的任何条目。 保留站可以包括用于确定存储在保留站的条目中的操作的相对年龄的年龄矩阵。 保留站可以包括选择逻辑，其被配置为基于存储在年龄矩阵中的值从保留站中选择最早的就绪操作。 选择逻辑可以利用控制逻辑来屏蔽对应于未就绪操作的年龄矩阵的列，以便确定哪个操作是保留站中的最早的就绪操作。 此外，保留站可以被配置为当这些操作没有负载依赖性时提前出队。

    Instruction loop buffer with tiered power savings
    15.
    发明授权
    Instruction loop buffer with tiered power savings 有权
    指令循环缓冲器，具有分层功率节省

    公开(公告)号：US09524011B2

    公开(公告)日：2016-12-20

    申请号：US14251508

    申请日：2014-04-11

    Applicant: Apple Inc.

    Inventor： Ronald P. Hall ,  Michael L. Karm ,  Ian D. Kountanis ,  David J. Williamson

    IPC: G06F1/26 ,  G06F1/32 ,  G06F9/00 ,  G06F9/30

    CPC classification number: G06F1/3234 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3844

    Abstract: Techniques are disclosed relating to power reduction during execution of instruction loops. Multiple different power saving modes may be used by a processor, such as a first power saving mode after only a few loop iterations (e.g., 2-3) and a second, deeper power saving mode after a greater number of loop iterations. The first power saving mode may include keeping a branch predictor and/or other structures active, but the second power saving mode may include reducing power to the branch predictor and/or other structures. An observation mode and an instruction capture mode may also be used by a processor prior to entering a power saving mode for loop execution. Power saving modes may also be achieved during execution of complex loops having multiple backward branches (e.g., nested loops).

    Abstract translation: 公开了在执行指令循环期间降低功率的技术。 处理器可以使用多种不同的功率节省模式，例如在更多数量的循环迭代之后仅仅几次循环迭代（例如2-3）和第二更深的省电模式之后的第一省电模式。 第一省电模式可以包括保持分支预测器和/或其他结构是有效的，但是第二省电模式可以包括降低分支预测器和/或其他结构的功率。 在进入用于循环执行的省电模式之前，处理器还可以使用观察模式和指令捕获模式。 在执行具有多个后向分支（例如，嵌套循环）的复杂环路时也可以实现节电模式。

    Multi-degree branch predictor
    16.
    发明授权
    Multi-degree branch predictor 有权

    公开(公告)号：US12236244B1

    公开(公告)日：2025-02-25

    申请号：US17810253

    申请日：2022-06-30

    Applicant: Apple Inc.

    Inventor： Wei-Han Lien ,  Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Niket K. Choudhary ,  Pruthivi Vuyyuru

    IPC: G06F9/38

    Abstract: A multi-degree branch predictor is disclosed. A processing circuit includes an instruction fetch circuit configured to fetch branch instructions, and a branch prediction circuit having a plurality of prediction subcircuits. The prediction subcircuits are configured to store different amounts of branch history data with respect to other ones, and to receive an indication of a given branch instruction in a particular clock cycle. The prediction subcircuits implement a common branch prediction scheme to output, in different clock cycles, corresponding predictions for the given branch instruction using the different amounts of branch history data and cause, instruction fetches to be performed by the instruction fetch circuit. The prediction subcircuits are also configured to override, in subsequent clock cycles, instruction fetches caused by prediction subcircuits with comparatively less branch history data based on contrary predictions performed in subsequent clock cycles by prediction subcircuits with more branch history data.

    Biased Conditional Instruction Prediction
    17.
    发明申请
    Biased Conditional Instruction Prediction 有权

    公开(公告)号：US20250036415A1

    公开(公告)日：2025-01-30

    申请号：US18358890

    申请日：2023-07-25

    Applicant: Apple Inc.

    Inventor： Deepankar Duggal ,  Pruthivi Vuyyuru ,  Ian D. Kountanis

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A processor may include a conditional instruction prediction tracking circuit. During fetch of a conditional instruction from memory to an instruction cache of the processor, the conditional instruction prediction tracking circuit may predict whether the conditional instruction is biased. Responsive to a prediction that the conditional instruction is biased, the conditional instruction prediction tracking circuit may cause the conditional instruction to be executed according to the predicted bias. Sometimes the conditional prediction tracking circuit may cause the conditional instruction to be re-coded such that it may be executed as an unconditional instruction.

    Conditional Instructions Distribution and Execution
    19.
    发明公开
    Conditional Instructions Distribution and Execution 审中-公开

    公开(公告)号：US20230244495A1

    公开(公告)日：2023-08-03

    申请号：US17590722

    申请日：2022-02-01

    Applicant: Apple Inc.

    Inventor： Ethan R. Schuchman ,  Niket K. Choudhary ,  Kulin N. Kothari ,  Haoyan Jia ,  Ian D. Kountanis ,  Douglas C. Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3844 ,  G06F9/3861 ,  G06F9/30145 ,  G06F9/30058 ,  G06F9/30079

    Abstract: A processor may include an instruction distribution circuit and a plurality of execution pipelines. The instruction distribution circuit may distribute a conditional instruction to a first execution pipeline for execution when the conditional instruction is associated with a prediction of a high confidence level, or to a second execution pipeline for execution when the conditional instruction is associated with a prediction of a low confidence level. The second execution pipeline, not the first execution pipeline, may directly instruct the processor to obtain an instruction from a target address for execution, when the conditional instruction is mispredicted. Thus, when the conditional instruction is distributed to the first execution pipeline for execution and determined to be mispredicted, the first execution pipeline may cause the conditional instruction to be re-executed in the second execution pipeline to cause the instruction from the correct target address to be obtained for execution.

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