公开(公告)号：US10417054B2

公开(公告)日：2019-09-17

申请号：US15870763

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/26 ,  G06F9/38 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/30 ,  G06F1/3206

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20180349182A1

公开(公告)日：2018-12-06

申请号：US15870766

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/54

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20180349175A1

公开(公告)日：2018-12-06

申请号：US15870760

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/26 ,  G06F9/50 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20150130422A1

公开(公告)日：2015-05-14

申请号：US14487061

申请日：2014-09-15

Applicant: Apple Inc.

Inventor： Eric Smith ,  Bryan R. Hinch ,  Tommee So

IPC: H02J7/00

CPC classification number: H02J7/007 ,  G06F1/263 ,  Y10T307/858

Abstract: Circuits, methods, and apparatus that may allow an electronic device to control a power adapter. One example may provide an electronic system where an electronic device may control a power adapter through a communication channel. Data transferred in the communication channel may include the temperature of the power adapter, the charging capability of the adapter, and other types of data. In one example, power and data may share the same two wires, and the power and data may be time-division multiplexed. That is, the two wires may convey power and data at different times. Another example may include circuitry to detect a connection between the electronic device and the power adapter. Once a connection is detected, power may be transferred from the power adapter to the electronic device. This power transfer may be interrupted on occasion to transfer data between the power adapter to the electronic device.

Abstract translation: 可允许电子设备控制电源适配器的电路，方法和设备。 一个示例可以提供电子系统，其中电子设备可以通过通信信道来控制电力适配器。 在通信信道中传送的数据可以包括电源适配器的温度，适配器的充电能力以及其他类型的数据。 在一个示例中，功率和数据可以共享相同的两条线，并且功率和数据可以被时分复用。 也就是说，两条线可以在不同时间传输电力和数据。 另一示例可以包括用于检测电子设备和电源适配器之间的连接的电路。 一旦检测到连接，电源可能会从电源适配器传输到电子设备。 这种电力传输有时可能会在电源适配器与电子设备之间传输数据。

公开(公告)号：US20220147132A1

公开(公告)日：2022-05-12

申请号：US17521567

申请日：2021-11-08

Applicant: Apple Inc.

Inventor： James S. Ismail ,  Bryan R. Hinch ,  Evan M. Hoke ,  Andrei Dorofeev ,  Shirin Dadashi ,  Mohsen Heidarinejad ,  Reza Araston

IPC: G06F1/3228 ,  G06F1/20 ,  G06F1/3215

Abstract: Embodiments are presented herein of, inter alia, systems, devices, and associated methods for allocating and distributing power management budgets for classes of tasks being executed by a computer system, based on thermal feedback loops. Specifically, multiple quality-of-service (QoS) tiers may be defined, and each QoS tier may be allocated power based on a different set of thermal feedback loops. QoS tiers including tasks that are invisible to the user may be mitigated more aggressively than QoS tiers including tasks that are visibly supporting user operations.

公开(公告)号：US20210349726A1

公开(公告)日：2021-11-11

申请号：US17384399

申请日：2021-07-23

Applicant: Apple Inc.

Inventor： Aditya Venkataraman ,  Bryan R. Hinch ,  John G. Dorsey

IPC: G06F9/38 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/48 ,  G06F9/50

Abstract: Closed loop performance controllers of asymmetric multiprocessor systems may be configured and operated to improve performance and power efficiency of such systems by adjusting control effort parameters that determine the dynamic voltage and frequency state of the processors and coprocessors of the system in response to the workload. One example of such an arrangement includes applying hysteresis to the control effort parameter and/or seeding the control effort parameter so that the processor or coprocessor receives a returning workload in a higher performance state. Another example of such an arrangement includes deadline driven control, in which the control effort parameter for one or more processing agents may be increased in response to deadlines not being met for a workload and/or decreased in response to deadlines being met too far in advance. The performance increase/decrease may be determined by comparison of various performance metrics for each of the processing agents.

公开(公告)号：US20210318909A1

公开(公告)日：2021-10-14

申请号：US17208928

申请日：2021-03-22

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US10658859B2

公开(公告)日：2020-05-19

申请号：US15714891

申请日：2017-09-25

Applicant: Apple Inc.

Inventor： Eric Smith ,  Bryan R. Hinch ,  Tommee So

IPC: H02J7/00 ,  G06F1/26

Abstract: Circuits, methods, and apparatus that may allow an electronic device to control a power adapter. One example may provide an electronic system where an electronic device may control a power adapter through a communication channel. Data transferred in the communication channel may include the temperature of the power adapter, the charging capability of the adapter, and other types of data. In one example, power and data may share the same two wires, and the power and data may be time-division multiplexed. That is, the two wires may convey power and data at different times. Another example may include circuitry to detect a connection between the electronic device and the power adapter. Once a connection is detected, power may be transferred from the power adapter to the electronic device. This power transfer may be interrupted on occasion to transfer data between the power adapter to the electronic device.

公开(公告)号：US20200073671A1

公开(公告)日：2020-03-05

申请号：US16376785

申请日：2019-04-05

Applicant: Apple Inc.

Inventor： Aditya Venkataraman ,  Bryan R. Hinch ,  John G. Dorsey

IPC: G06F9/38 ,  G06F9/48 ,  G06F1/3296 ,  G06F1/3228

Abstract: Closed loop performance controllers of asymmetric multiprocessor systems may be configured and operated to improve performance and power efficiency of such systems by adjusting control effort parameters that determine the dynamic voltage and frequency state of the processors and coprocessors of the system in response to the workload. One example of such an arrangement includes applying hysteresis to the control effort parameter and/or seeding the control effort parameter so that the processor or coprocessor receives a returning workload in a higher performance state. Another example of such an arrangement includes deadline driven control, in which the control effort parameter for one or more processing agents may be increased in response to deadlines not being met for a workload and/or decreased in response to deadlines being met too far in advance. The performance increase/decrease may be determined by comparison of various performance metrics for each of the processing agents.

公开(公告)号：US20180349186A1

公开(公告)日：2018-12-06

申请号：US15870764

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/48 ,  G06F9/50

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.