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公开(公告)号：US20240004664A1
公开(公告)日：2024-01-04
申请号：US17855727
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Sree Harsha Kosuru , Eric Dixon , Erik Swanson , Michael Estlick , Patrick Michael Lowry
CPC classification number: G06F9/384 , G06F9/30123
Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US11573801B1
公开(公告)日：2023-02-07
申请号：US17489301
申请日：2021-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Eric Dixon , Erik Swanson , Theodore Carlson , Ruchir Dalal , Michael Estlick
Abstract: A processor includes a register file and control logic that detects multiple different sets of sequential zero bits of a register in the register file, wherein each of the multiple different sets has a bit length that corresponds to a partial instruction width and operates at a first partial instruction width or a second partial instruction width with the register file depending on number of sets of zero bits detected in the register. In certain examples, the control logic causes operating at first instruction width that avoids merging of a first bit length of data in the register and operating at the second instruction width that avoids merging of a second bit length of data in the register. In some examples, a register rename map table incudes multiple zero bits that identify the detected multiple different sets of bits of sequential zeros.
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公开(公告)号：US11544065B2
公开(公告)日：2023-01-03
申请号：US16585817
申请日：2019-09-27
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Arun A. Nair , Todd Baumgartner , Michael Estlick , Erik Swanson
IPC: G06F9/30
Abstract: A processor includes a front-end with an instruction set that operates at a first bit width and a floating point unit coupled to receive the instruction set in the processor that operates at the first bit width. The floating point unit operates at a second bit width and, based upon a bit width assessment of the instruction set provided to the floating point unit, the floating point unit employs a shadow-latch configured floating point register file to perform bit width reconfiguration. The shadow-latch configured floating point register file includes a plurality of regular latches and a plurality of shadow latches for storing data that is to be either read from or written to the shadow latches. The bit width reconfiguration enables the floating point unit that operates at the second bit width to operate on the instruction set received at the first bit width.
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14.发明授权公开(公告)号：US10776123B2
公开(公告)日：2020-09-15
申请号：US16207548
申请日：2018-12-03
Applicant: Advanced Micro Devices, Inc.
Inventor： Erik D. Swanson , Michael Estlick , Sneha V. Desai
IPC: G06F9/38
Abstract: Systems, apparatuses, and methods for performing efficient processor pipeline flush recovery are disclosed. A processor core includes a retire queue for storing information of outstanding instructions. When the retire queue logic detects that a pipeline flush condition occurs, the logic creates one or more groups of entries in the retire queue. The logic begins the groups with an entry storing information for a youngest outstanding instruction, and creates other groups in a contiguous manner after creating this first group. The logic marks with a first indication a given group when the given group includes one or more instructions of a given type. The logic marks with a second indication the given group when the given group does not include an instruction of the given type. The logic sends to flush recovery logic information of one or more entries in only groups marked with the first indication.
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公开(公告)号：US20200174796A1
公开(公告)日：2020-06-04
申请号：US16207548
申请日：2018-12-03
Applicant: Advanced Micro Devices, Inc.
Inventor： Erik D. Swanson , Michael Estlick , Sneha V. Desai
Abstract: Systems, apparatuses, and methods for performing efficient processor pipeline flush recovery are disclosed. A processor core includes a retire queue for storing information of outstanding instructions. When the retire queue logic detects that a pipeline flush condition occurs, the logic creates one or more groups of entries in the retire queue. The logic begins the groups with an entry storing information for a youngest outstanding instruction, and creates other groups in a contiguous manner after creating this first group. The logic marks with a first indication a given group when the given group includes one or more instructions of a given type. The logic marks with a second indication the given group when the given group does not include an instruction of the given type. The logic sends to flush recovery logic information of one or more entries in only groups marked with the first indication.
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Patent Agency Ranking
公开(公告)号：US09575763B2
公开(公告)日：2017-02-21
申请号：US13918863
申请日：2013-06-14
Applicant: Advanced Micro Devices, Inc.
Inventor： Jay Fleischman , Michael Estlick
CPC classification number: G06F9/384 , G06F9/3842 , G06F9/3859 , G06F9/3861
Abstract: A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and concurrently deallocating resources previously allocated to the speculative instructions in response to interruption of dispatch of instructions due to a flush of the speculative instructions. A processor device comprises a retire queue to store entries for instructions that are awaiting retirement and a finite state machine. The finite state machine is to interrupt dispatch of instructions in response to a flush of speculative instructions previously dispatched for execution in the processing device and to undo, in reverse program order, changes in a state of the processing device caused by the speculative instructions while concurrently deallocating resources previously allocated to the speculative instructions.
Abstract translation: 一种方法包括以反向程序顺序来撤销由先前在处理设备中执行的推测性指令引起的处理设备的状态的改变，并且响应于由于指令的发送中断而先前分配给推测指令的资源 冲突的投机指示。 处理器设备包括用于存储等待退休的指令的条目的退出队列和有限状态机。 有限状态机是响应于先前调度以在处理设备中执行的推测性指令的刷新来中断指令的分派，并且以反向程序顺序撤销由推测指令引起的处理设备的状态的改变，同时 释放以前分配给投机指示的资源。
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公开(公告)号：US12229563B2
公开(公告)日：2025-02-18
申请号：US17855727
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Sree Harsha Kosuru , Eric Dixon , Erik Swanson , Michael Estlick , Patrick Michael Lowry
Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US12223324B2
公开(公告)日：2025-02-11
申请号：US17957604
申请日：2022-09-30
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Michael Estlick , Eric Dixon , Theodore Carlson , Erik D. Swanson
Abstract: A data processing system includes a vector data processing unit that includes a shared scheduler queue configured to store in a same queue, at least one entry that includes at least a mask type instruction and another entry that includes at least a vector type instruction. Shared pipeline control logic controls a vector data path or a mask data path, based a type of instruction picked from the same queue. In some examples, at least one mask type instruction and the at least one vector type instruction each include a source operand having a corresponding shared source register bit field that indexes into both a mask register file and a vector register file. The shared pipeline control logic uses a mask register file or a vector register file depending on whether bits of the shared source register bit field identify a mask source register or a vector source register.
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公开(公告)号：US12204935B2
公开(公告)日：2025-01-21
申请号：US17390149
申请日：2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael Estlick , Erik Swanson , Eric Dixon
Abstract: Methods, systems, and apparatuses provide support for allowing thread forward progress in a processing system and that improves quality of service. One system includes a processor; a bus coupled to the processor; a memory coupled to the processor via the bus; and a floating point unit coupled to the processor via the bus, wherein floating point unit comprises hardware control logic operative to: store for each thread, by a scheduler of the floating point unit, a counter; increase, by the scheduler, a value of the counter for each thread corresponding to a thread when at least one source ready operation exist for the thread; compare, by the scheduler, the value of the counter to a predetermined threshold; and make other threads ineligible to be picked by the scheduler when the counter is greater than or equal to the predetermined threshold.
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公开(公告)号：US11907070B2
公开(公告)日：2024-02-20
申请号：US17390293
申请日：2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Eric Busta , Michael L. Golden , Sean M. O′Mullan , James Wingfield , Keith A. Kasprak , Russell Schreiber , Michael Estlick
CPC classification number: G06F11/1417 , G06F9/3013 , G06F9/5011 , G06F11/0772
Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.
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