公开(公告)号：US11726839B2

公开(公告)日：2023-08-15

申请号：US17446796

申请日：2021-09-02

Applicant: Arm Limited

Inventor： Mark Salling Rutland ,  Gareth Rhys Stockwell ,  Christoffer Dall ,  Jade Ella Carla Alglave

IPC: G06F9/52 ,  G06F9/48

CPC classification number: G06F9/524 ,  G06F9/4881

Abstract: Apparatus comprises a data memory to store lock data for each of a set of processing resources, the lock data representing lock status data and tag data indicating a resource type selected from a plurality of resource types; and a processing element to execute an atomic operation with respect to the lock data for a given processing resource, the atomic operation comprising at least: a detection of whether the given processing resource is of a required resource type; a detection from the lock status data whether the given processing resource is currently unlocked; and when the given processing resource is detected to be currently unlocked and of the required resource type, performance of a predetermined action with respect to one or both of the lock status data and the tag data.

公开(公告)号：US11176061B2

公开(公告)日：2021-11-16

申请号：US16623922

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Gareth Rhys Stockwell ,  Jason Parker ,  Matthew Lucien Evans ,  Martin Weidmann

IPC: G06F12/14

Abstract: Memory access circuitry (26) enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry (8). The owner realm has a right to exclude other realms from accessing data within the memory region. Realm management circuitry (20) accesses a realm management tree storing realm management data for at least two realms in a tree structure having a variable number of levels. The realms are identified using a realm identifier which has a variable number of variable length bit portions each providing an index into a given level of the realm management tree.

公开(公告)号：US11086659B2

公开(公告)日：2021-08-10

申请号：US16623569

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Matthew Lucien Evans ,  Jason Parker ,  Gareth Rhys Stockwell ,  Martin Weidmann

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/46 ,  G06F12/14

Abstract: Processing circuitry (8) processes software processes at one of a plurality of exception levels and in one of a plurality of realms, each realm corresponding to a portion of at least one software process and being associated with a boundary exception level indicating a most privileged exception level at which the realm can be processed by the processing circuitry (8). In response to a realm exiting exception condition during processing of a given realm, where the exception condition is to be handled by an exception handler at a more privileged exception level than the boundary exception level of the given realm, the processing circuitry (8) performs state masking to make inaccessible, to software processes processed at a more privileged exception level than the boundary exception level, architectural state of a subset of registers selected depending on the boundary exception level of the given realm.

公开(公告)号：US11016910B2

公开(公告)日：2021-05-25

申请号：US16623999

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Djordje Kovacevic ,  Jason Parker ,  Matthew Lucien Evans ,  Gareth Rhys Stockwell

IPC: G06F12/14 ,  G06F12/10 ,  G06Q10/10

Abstract: Apparatus for processing data uses memory access circuitry to enforce ownership rights of a plurality of memory regions within a memory, a given memory region among the plurality of memory regions having a given owning process specified from among a plurality of processes. A given owning process has exclusive rights to control access to given owned data stored within the given memory region. The memory access circuitry is responsive to a first access command from a first processing element for the given memory region to perform an access sequence comprising switching a lock flag for the given memory region to a locked state, performing an access operation specified by the access command, and switching the lock flag to an unlocked state. The memory access circuitry is responsive to a second access command from a second processing element for the given memory region while the lock flag is in said locked state to block action of the second access command.