公开(公告)号：US10445000B2

公开(公告)日：2019-10-15

申请号：US15320380

申请日：2015-05-19

Applicant: ARM LIMITED

Inventor： Irenéus Johannes De Jong ,  Andreas Hansson

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G06F9/46 ,  G06F12/0802 ,  G06F12/10 ,  G06F13/00 ,  G06F13/28

Abstract: A device controller and method are provided for performing a plurality of write transactions atomically within a non-volatile data storage device. Each transaction specifies a logical address and the method comprises creating an address translation map for the logical addresses specified by the plurality of write transactions, by referencing an address translation record within the non-volatile data storage device to determine for each logical address a corresponding physical address within the data storage device. Further, if the corresponding physical address indicated in the address translation record already contains valid data, the logical address is remapped to a new physical address in the address translation map. However, at this point the address translation record as stored in the data storage device is not updated. Instead, the plurality of write transactions are performed using the logical address to physical address mapping in the address translation map. Then, only once the plurality of write transactions have been performed is the address translation record updated in the non-volatile data storage device in order to identify the logical address to physical address mapping in the address translation map. Since, at the time of performing the write transactions, any new data that updates data already stored in the data storage device is written into a different physical address location, and hence the previous version of the data is still stored on the data storage device, and given that the address translation record is not updated unless the plurality of write transactions are actually performed atomically, then this enables the state held on the data storage device to be rolled back to the state that existed prior to performing the plurality of write transactions, if any event prevents that plurality of write transactions being performed atomically.

公开(公告)号：US10181350B2

公开(公告)日：2019-01-15

申请号：US15842207

申请日：2017-12-14

Applicant: ARM Limited

Inventor： Shidhartha Das ,  Andreas Hansson ,  Akshay Kumar ,  Piyush Agarwal ,  Azeez Jennudin Bhavnagarwala ,  Lucian Shifren

IPC: G11C11/00 ,  G11C13/00

Abstract: A method of writing a state to a correlated electron element in a storage circuit, comprising receiving a write command to write the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver to write the state into the correlated electron element when the state and read state are different.

公开(公告)号：US10133675B2

公开(公告)日：2018-11-20

申请号：US15325250

申请日：2015-06-22

Applicant: ARM LIMITED

Inventor： Andreas Hansson ,  Ali Saidi ,  Aniruddha Nagendran Udipi ,  Stephan Diestelhorst

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1027

Abstract: A data processing apparatus and method are provided for performing address translation in response to a memory access request issued by processing circuitry of the data processing apparatus and specifying a virtual address for a data item. Address translation circuitry performs an address translation process with reference to at least one descriptor provided by at least one page table, in order to produce a modified memory access request specifying a physical address for the data item. The address translation circuitry includes page table walk circuitry configured to generate at least one page table walk request in order to retrieve the at least one descriptor required for the address translation process. In addition, walk ahead circuitry is located in a path between the address translation circuitry and a memory device containing the at least one page table. The walk ahead circuitry comprises detection circuitry used to detect a memory page table walk request generated by the page table walk circuitry of the address translation circuitry for a descriptor in a page table. In addition, the walk ahead circuitry has further request generation circuitry which is used to generate a prefetch memory request in order to prefetch data from the memory device at a physical address determined with reference to the descriptor requested by the detected memory page table walk request. This prefetched data may be another descriptor required as part of the address translation process, or may be the actual data item being requested by the processing circuitry. Such an approach can significantly reduce latency associated with the address translation process.

公开(公告)号：US09218285B2

公开(公告)日：2015-12-22

申请号：US13684700

申请日：2012-11-26

Applicant: ARM LIMITED

Inventor： Anirruddha Nagendran Udipi ,  Ali Saidi ,  Andreas Hansson ,  Christopher Emmons

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G11C7/04 ,  G11C11/406 ,  G11C11/408

CPC classification number: G06F12/0292 ,  G06F12/0238 ,  G06F12/06 ,  G06F12/0646 ,  G06F12/08 ,  G11C7/04 ,  G11C11/40622 ,  G11C11/40626 ,  G11C11/408

Abstract: An apparatus for processing data 2 includes a memory 4 having a plurality of memory regions 28 to 38. A mapping controller 56 applies a variable mapping to map memory addresses of access requests to different regions within the memory 4. The mapping controller varies the mapping applied in dependence upon both one or more memory behavioral parameters indicative of behavioral characteristics of the different regions and one or more access behavioral parameters indicative of behavioral characteristics of an access request to be mapped. The memory behavioral parameters may include the temperature of the regions and/or the refresh period of the regions. The access behavior able parameters may include the quality of service level, the access frequency, the access volume and/or the identity of the source of the access request.

Abstract translation: 一种用于处理数据2的装置包括具有多个存储器区域28至38的存储器4.映射控制器56应用可变映射将访问请求的存储器地址映射到存储器4内的不同区域。映射控制器改变应用的映射 依赖于指示不同区域的行为特征的一个或多个存储器行为参数以及指示要映射的访问请求的行为特征的一个或多个访问行为参数。 存储器行为参数可以包括区域的温度和/或区域的刷新周期。 访问行为能力参数可以包括服务质量水平，访问频率，访问量和/或访问请求的来源的身份。