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公开(公告)号：US09454397B2
公开(公告)日：2016-09-27
申请号：US14682302
申请日：2015-04-09
Applicant: ARM Limited
Inventor： Hakan Persson , Matt Evans , Jason Parker , Marc Zyngier
CPC classification number: G06F9/45558 , G06F9/4405 , G06F9/4411 , G06F2009/45579
Abstract: A data processing system includes one or more processors that each execute one or more operating systems that include one or more applications; an accelerator that provides a shared resource for a plurality of the applications; a storage area accessible by the processors and the accelerator; and one or more input/output interfaces for control of, or the submission of tasks to, the accelerator. To initialize one of the input/output interfaces, one of the one or more processors is capable of sending a first signal to the accelerator; the accelerator is capable of writing one or more selected pieces of information representative of one or more capabilities of the accelerator to the storage area and sending a second signal to the processor; the processor is capable of reading the one or more selected pieces of information from the storage area; and the accelerator is capable of configuring the input/output interface.
Abstract translation: 数据处理系统包括一个或多个处理器，每个处理器执行包括一个或多个应用的一个或多个操作系统; 提供用于多个应用的共享资源的加速器; 由处理器和加速器可访问的存储区域; 以及一个或多个输入/输出接口，用于控制或提交加速器的任务。 为了初始化输入/输出接口之一，一个或多个处理器之一能够向加速器发送第一信号; 加速器能够将表示加速器的一个或多个能力的一个或多个选定的信息段写入存储区域，并向处理器发送第二信号; 处理器能够从存储区域读取一个或多个所选择的信息; 并且加速器能够配置输入/输出接口。
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公开(公告)号：US12147355B2
公开(公告)日：2024-11-19
申请号：US17906581
申请日：2021-01-26
Applicant: Arm Limited
Inventor： Jason Parker , Yuval Elad
IPC: G06F12/14 , G06F12/1009 , G06F12/109
Abstract: Processing circuitry (10) performs processing in one of at least three domains (82, 84, 86, 88). Address translation circuitry (16) translates a virtual address of a memory access performed from a current domain to a physical address in one of a plurality of physical address spaces (61) selected based at least on the current domain. The domains include a root domain (82) for managing switching between other domains. The physical address spaces (61) include a root physical address space associated with the root domain (82), separate from physical address spaces associated with other domains.
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公开(公告)号：US11874778B2
公开(公告)日：2024-01-16
申请号：US16625943
申请日：2018-06-11
Applicant: ARM LIMITED
Inventor： Jason Parker , Matthew Lucien Evans , Gareth Rhys Stockwell , Djordje Kovacevic
CPC classification number: G06F12/1458 , G06F12/0253 , G06F21/6218 , G06F2212/1044
Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. A realm management unit (RMU) is provided to perform realm management operations for managing the realms. The memory access circuitry controls access to a given memory region in dependence on at least one status attribute specifying whether the given memory region is an RMU-private memory region reserved for exclusive access by the RMU.
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公开(公告)号：US10942739B2
公开(公告)日：2021-03-09
申请号：US15571952
申请日：2016-04-12
Applicant: ARM Limited
Inventor： Jason Parker
Abstract: A data processing apparatus and method of data processing are provided which make use of a processor state check instruction to determine if the data processing apparatus is currently operating in a processor state, defined by at least one runtime processor state configuration value, which matches a processor state check value defined by the processor state check instruction. Dependent on the required runtime processor state configuration value(s) matching the processor state check value, the processor state check instruction is treated as an ineffective instruction. When the at least one runtime processor state configuration value does not match the processor state check value an exception is generated. Improved security of the data processing apparatus is thus provided.
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公开(公告)号：US10936504B2
公开(公告)日：2021-03-02
申请号：US15579665
申请日：2016-04-28
Applicant: ARM Limited
Inventor： Jason Parker , Richard Roy Grisenthwaite , Andrew Christopher Rose
IPC: G06F12/10 , G06F12/1009 , G06F9/46 , G06F21/72 , G06F21/78 , G06F12/1036 , G06F12/14 , G06F12/1018
Abstract: A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).
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Patent Agency Ranking
公开(公告)号：US10558486B2
公开(公告)日：2020-02-11
申请号：US16066382
申请日：2016-12-21
Applicant: ARM LIMITED
Inventor： Jason Parker
IPC: G06F12/00 , G06F9/455 , G06F12/1009 , G06F11/07 , G06F12/1027 , G06F13/00 , G06F13/28
Abstract: A data processing apparatus (2) includes memory management circuitry (18) for managing a two-stage address translation from a virtual address VA to an intermediate physical address IPA and then from the intermediate physical address IPA to a physical address PA. The first stage of the translation is performed using first stage translation data (22) controlled by a virtual machine program executing within a virtual machine execution environment provided by a hypervisor program which manages second stage translation data (24) for performing a second stage translation. If a region of memory is designated as a virtual machine private region accessible to a given virtual machine, but inaccessible to the hypervisor program, and also as a device region, then the memory management circuitry (18) performs private-device region management in respect of that region (i.e. the intermediate physical address may not be altered by the second stage translation). If a region is not both a virtual machine private region and a device region, then the memory management circuitry (18) performs non-private device management thereon.
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公开(公告)号：US20150293774A1
公开(公告)日：2015-10-15
申请号：US14682302
申请日：2015-04-09
Applicant: ARM LIMITED
Inventor： Hakan Persson , Matt Evans , Jason Parker , Marc Zyngier
CPC classification number: G06F9/45558 , G06F9/4405 , G06F9/4411 , G06F2009/45579
Abstract: A data processing system includes one or more processors that each execute one or more operating systems that include one or more applications; an accelerator that provides a shared resource for a plurality of the applications; a storage area accessible by the processors and the accelerator; and one or more input/output interfaces for control of, or the submission of tasks to, the accelerator. To initialise one of the input/output interfaces, one of the one or more processors is capable of sending a first signal to the accelerator; the accelerator is capable of writing one or more selected pieces of information representative of one or more capabilities of the accelerator to the storage area and sending a second signal to the processor; the processor is capable of reading the one or more selected pieces of information from the storage area; and the accelerator is capable of configuring the input/output interface.
Abstract translation: 数据处理系统包括一个或多个处理器，每个处理器执行包括一个或多个应用的一个或多个操作系统; 提供用于多个应用的共享资源的加速器; 由处理器和加速器可访问的存储区域; 以及一个或多个输入/输出接口，用于控制或提交加速器的任务。 为了初始化输入/输出接口之一，一个或多个处理器之一能够向加速器发送第一信号; 加速器能够将表示加速器的一个或多个能力的一个或多个选定的信息段写入存储区域，并向处理器发送第二信号; 处理器能够从存储区域读取一个或多个所选择的信息; 并且加速器能够配置输入/输出接口。
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公开(公告)号：US12271320B2
公开(公告)日：2025-04-08
申请号：US17906625
申请日：2021-01-26
Applicant: ARM LIMITED
Inventor： Jason Parker , Andrew Brookfield Swaine , Yuval Elad , Martin Weidmann
IPC: G06F12/14 , G06F12/0808 , G06F12/1045
Abstract: Address translation circuitry (16) translates a virtual address specified by a memory access request issued by requester circuitry into a target physical address (PA). Requester-side filtering circuitry (20) performs a granule protection lookup based on the target PA and a selected physical address space (PAS) associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or interconnect. In the granule protection lookup, the requester-side filtering circuitry obtains granule protection information corresponding to a target granule of physical addresses including the target PA, which indicates at least one allowed PAS associated with the target granule, and blocks the memory access request when the granule protection information indicates that the selected PAS is not an allowed PAS.
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公开(公告)号：US11989134B2
公开(公告)日：2024-05-21
申请号：US17907178
申请日：2021-03-08
Applicant: ARM LIMITED
Inventor： Yuval Elad , Jason Parker , Richard Roy Grisenthwaite , Simon John Craske , Alexander Donald Charles Chadwick
CPC classification number: G06F12/10 , G06F3/0622 , G06F3/0637 , G06F3/0673
Abstract: An apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.
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公开(公告)号：US11914522B2
公开(公告)日：2024-02-27
申请号：US17907206
申请日：2021-02-08
Applicant: ARM LIMITED
Inventor： Jason Parker
IPC: G06F12/10 , G06F12/1027 , G06F12/14
CPC classification number: G06F12/10 , G06F12/1027 , G06F12/14 , G06F2212/1032
Abstract: Apparatuses, methods, and programs for performing a translation of a virtual address of a memory access to a physical address associated with a memory location to be accessed are disclosed. A page table descriptor is accessed when performing the translation, which comprises translation parameters for the translation. The descriptor further comprises an integrity check value, wherein the integrity check value is dependent on the translation parameters.
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