公开(公告)号：US20230101155A1

公开(公告)日：2023-03-30

申请号：US17868156

申请日：2022-07-19

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Fred Fishburn ,  Tomohiko Kitajima ,  Sung-Kwan Kang ,  Sony Varghese ,  Gill Yong Lee

IPC: H01L27/108

Abstract: A memory device architecture, and method of fabricating a three dimensional device are provided. The memory device architecture may include a plurality of memory blocks, arranged in an array, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells, arranged in a plurality of n memory cell layers; and a staircase region, the staircase region being disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly that is coupled to the three-dimensional array of memory cells.

公开(公告)号：US20220108728A1

公开(公告)日：2022-04-07

申请号：US17551538

申请日：2021-12-15

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sanjay Natarajan ,  Sung-Kwan Kang ,  Lequn Liu

IPC: G11C5/06 ,  H01L27/108

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

公开(公告)号：US10964717B2

公开(公告)日：2021-03-30

申请号：US16528800

申请日：2019-08-01

Applicant: APPLIED MATERIALS, INC.

Inventor： Sung-Kwan Kang ,  Gill Lee ,  Chang Seok Kang ,  Tomohiko Kitajima

IPC: H01L27/11582 ,  H01L21/67 ,  H01L21/768 ,  H01L21/311

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming, on a substrate, a stack of alternating layers including a first layer of material and a second layer of material different from the first layer of material; forming a memory hole in the stack of alternating layers of the first layer of material and the second layer of material; depositing a layer of blocking oxide on sides defining the memory hole; depositing a layer of silicon atop the layer of blocking oxide to form a silicon channel; deposit core oxide to fill the silicon channel; removing the first layer of material to form spaces between the alternating layers of the second material; and one of depositing a third layer of material to partially fill the spaces to leave air gaps therein or depositing a fourth layer of material to fill the spaces.

公开(公告)号：US20200235104A1

公开(公告)日：2020-07-23

申请号：US16839392

申请日：2020-04-03

Applicant: Applied Materials, Inc.

Inventor： Priyadarshi Panda ,  Jianxin Lei ,  Wenting Hou ,  Mihaela Balseanu ,  Ning Li ,  Sanjay Natarajan ,  Gill Yong Lee ,  In Seok Hwang ,  Nobuyuki Sasaki ,  Sung-Kwan Kang

IPC: H01L27/108 ,  H01L21/3213 ,  H01L21/033

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.

公开(公告)号：US20230157004A1

公开(公告)日：2023-05-18

申请号：US18096923

申请日：2023-01-13

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Nitin K. Ingle ,  Sung-Kwan Kang

IPC: H10B12/00 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC classification number: H10B12/30 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1222 ,  H01L27/1255 ,  H01L29/6675 ,  H01L29/42392 ,  H01L29/78672 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

公开(公告)号：US11552082B2

公开(公告)日：2023-01-10

申请号：US17002415

申请日：2020-08-25

Applicant: Applied Materials, Inc.

Inventor： Sung-Kwan Kang ,  Gill Yong Lee ,  Sang Ho Yu ,  Shih Chung Chen ,  Jeffrey W. Anthis

IPC: H01L21/3213 ,  H01L21/28 ,  H01L21/321 ,  H01L21/02 ,  H01L27/108 ,  H01L29/49 ,  H01L29/423

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.

公开(公告)号：US11430801B2

公开(公告)日：2022-08-30

申请号：US17227925

申请日：2021-04-12

Applicant: APPLIED MATERIALS, INC.

Inventor： Takehito Koshizawa ,  Mukund Srinivasan ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Sung-Kwan Kang ,  Gill Y. Lee ,  Susmit Singha Roy

IPC: H01L27/1157 ,  H01L27/11582

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.

公开(公告)号：US20220068935A1

公开(公告)日：2022-03-03

申请号：US17522448

申请日：2021-11-09

Applicant: Applied Materials, Inc.

Inventor： Priyadarshi Panda ,  Seshadri Ganguli ,  Sang Ho Yu ,  Sung-Kwan Kang ,  Gill Yong Lee ,  Sanjay Natarajan ,  Rajib Lochan Swain ,  Jorge Pablo Fernandez

IPC: H01L27/108

Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

公开(公告)号：US20210249415A1

公开(公告)日：2021-08-12

申请号：US17159534

申请日：2021-01-27

Applicant: Applied Materials, Inc.

Inventor： CHANG SEOK KANG ,  Tomohiko Kitajima ,  Nitin K. Ingle ,  Sung-Kwan Kang

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

公开(公告)号：US10998329B2

公开(公告)日：2021-05-04

申请号：US16517956

申请日：2019-07-22

Applicant: APPLIED MATERIALS, INC.

Inventor： Takehito Koshizawa ,  Mukund Srinivasan ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Sung-Kwan Kang ,  Gill Y. Lee ,  Susmit Singha Roy

IPC: H01L27/1157 ,  H01L27/11582

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.