公开(公告)号：US11621266B2

公开(公告)日：2023-04-04

申请号：US17522448

申请日：2021-11-09

Applicant: Applied Materials, Inc.

Inventor： Priyadarshi Panda ,  Seshadri Ganguli ,  Sang Ho Yu ,  Sung-Kwan Kang ,  Gill Yong Lee ,  Sanjay Natarajan ,  Rajib Lochan Swain ,  Jorge Pablo Fernandez

IPC: H01L21/67 ,  H01L27/108

Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

公开(公告)号：US11587930B2

公开(公告)日：2023-02-21

申请号：US17159534

申请日：2021-01-27

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Nitin K. Ingle ,  Sung-Kwan Kang

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

公开(公告)号：US20230040627A1

公开(公告)日：2023-02-09

申请号：US17879097

申请日：2022-08-02

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sung-Kwan Kang

IPC: H01L27/11524 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Described is a semiconductor memory device and methods of manufacture. The semiconductor memory device comprises a memory array comprising at least one select-gate-for-drain (SGD) transistor and at least one memory transistor, the memory array having at least one strapping region and at least one strapping contact, the strapping contact connecting a select-gate-for-drain (SGD) transistor to a strapping line.

公开(公告)号：US20220415651A1

公开(公告)日：2022-12-29

申请号：US17361925

申请日：2021-06-29

Applicant: Applied Materials, Inc.

Inventor： Qixin Shen ,  Chuanxi Yang ,  Hang Yu ,  Deenesh Padhi ,  Gill Yong Lee ,  Sung-Kwan Kang ,  Abdul Wahab Mohammed ,  Hailing Liu

IPC: H01L21/02 ,  H01L21/033 ,  H01L27/108

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.

公开(公告)号：US20220352176A1

公开(公告)日：2022-11-03

申请号：US17727907

申请日：2022-04-25

Applicant: Applied Materials, Inc.

Inventor： Sung-Kwan Kang ,  Fredrick Fishburn ,  Abdul Wahab Mohammed ,  Gill Yong Lee

IPC: H01L27/108

Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where a spacer is formed around each of the bit line contact pillars, the spacer in contact with the spacer of an adjacent bit line contact pillar. A doped layer is then epitaxially grown on the memory stack and bit line is formed on the memory stack. The bit line is self-aligned with the active region.

公开(公告)号：US20210233779A1

公开(公告)日：2021-07-29

申请号：US17147578

申请日：2021-01-13

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Sung-Kwan Kang

IPC: H01L21/321 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11582

Abstract: Memory devices and methods of manufacturing memory devices are provided. The device and methods described suppress oxidation of metal layers exposed to ambient oxygen. After an opening is formed, a nitridation process occurs to nitridate the surface of the exposed metal layer inside the opening. The nitridated region formed on the surface of metal layer inside the opening works as a barrier layer for oxygen diffusion. In addition, the nitridated region works as an electrode for charge trap memory cells.

公开(公告)号：US20200251151A1

公开(公告)日：2020-08-06

申请号：US16779830

申请日：2020-02-03

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sanjay Natarajan ,  Sung-Kwan Kang ,  Lequn Liu

IPC: G11C5/06 ,  H01L27/108

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

公开(公告)号：US20240315004A1

公开(公告)日：2024-09-19

申请号：US18186091

申请日：2023-03-17

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Sung-Kwan Kang

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482 ,  H10B12/488

Abstract: A 4F2 two-dimensional dynamic random access memory array may include vertical pillar transistors that are arranged in a honeycomb pattern to maximize the available capacitor footprint on top of the memory array. The bit lines may partially intersect with bottom source/drain regions of two adjacent columns of the vertical transistors, where the columns may be offset based on the honeycomb pattern. The word lines may have a varying width that increases as the word lines enclose the gate regions of the transistors and that decreases between adjacent transistors. The transistor stages may each be formed individually and incrementally, with the bottom source/drain region and the bit lines being completed first, followed by the gate region and the word lines, followed by the top source/drain regions and the capacitors.

公开(公告)号：US11818877B2

公开(公告)日：2023-11-14

申请号：US17486631

申请日：2021-09-27

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Sung-Kwan Kang ,  Fredrick Fishburn ,  Gill Yong Lee ,  Nitin K. Ingle

IPC: H10B12/00

CPC classification number: H10B12/05 ,  H10B12/03 ,  H10B12/30

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

公开(公告)号：US11749315B2

公开(公告)日：2023-09-05

申请号：US17551538

申请日：2021-12-15

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sanjay Natarajan ,  Sung-Kwan Kang ,  Lequn Liu

IPC: G11C5/06 ,  H10B12/00

CPC classification number: G11C5/063 ,  H10B12/02 ,  H10B12/03 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/30 ,  H10B12/318 ,  H10B12/482 ,  H10B12/488

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.