公开(公告)号：US20180350621A1

公开(公告)日：2018-12-06

申请号：US15995698

申请日：2018-06-01

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Shishi JIANG ,  Abhijit Basu MALLICK ,  Kurtis LESCHKIES

IPC: H01L21/311 ,  H01L21/02

Abstract: Embodiments of the disclosure generally relate to a method for dry stripping a boron carbide layer deposited on a semiconductor substrate. In one embodiment, the method includes loading the substrate with the boron carbide layer into a pressure vessel, exposing the substrate to a processing gas comprising an oxidizer at a pressure between about 500 Torr and 60 bar, heating the pressure vessel to a temperature greater than a condensation point of the processing gas and removing one or more products of a reaction between the processing gas and the boron carbide layer from the pressure vessel.

公开(公告)号：US20180350563A1

公开(公告)日：2018-12-06

申请号：US15991877

申请日：2018-05-29

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Abhijit Basu MALLICK ,  Kurtis LESCHKIES ,  Steven VERHAVERBEKE ,  Sanjay KAMATH ,  Zongbin WANG ,  Hanwen ZHANG ,  Shishi JIANG

IPC: H01J37/32

Abstract: Embodiments of the disclosure generally relate to a method of processing a semiconductor substrate at a temperature less than 250 degrees Celsius. In one embodiment, the method includes loading the substrate with the deposited film into a pressure vessel, exposing the substrate to a processing gas comprising an oxidizer at a pressure greater than about 2 bars, and maintaining the pressure vessel at a temperature between a condensation point of the processing gas and about 250 degrees Celsius.

公开(公告)号：US20180337061A1

公开(公告)日：2018-11-22

申请号：US15599920

申请日：2017-05-19

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Steven VERHAVERBEKE ,  Ziqing DUAN ,  Abhijit Basu MALLICK

IPC: H01L21/32 ,  H01L21/306

Abstract: Embodiments described herein generally relate methods for selective deposition of carbon structures. In one embodiment, a method includes forming energized carbon species in a process chamber, diffusing the energized carbon species through a metal layer, wherein the metal layer is disposed on a first surface of a first material that is coplanar with a second surface of a second material, and forming a carbon structure between the first surface of the first material and the metal layer from the energized carbon species. Because the carbon structure is selectively deposited on the first surface and self-aligned to the first material, the possibility of overlay or misalignment of subsequent device layers formed on the first surface of the first material after the removal of the carbon structure is significantly reduced.

公开(公告)号：US20170148624A1

公开(公告)日：2017-05-25

申请号：US15325419

申请日：2015-07-10

Applicant: Applied Materials, Inc.

Inventor： Steven VERHAVERBEKE ,  Han-Wen CHEN ,  Roman GOUK ,  Kurtis LESCHKIES

IPC: H01L21/02 ,  H01L21/67

CPC classification number: H01L21/0206 ,  H01J37/32357 ,  H01L21/02101 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02334 ,  H01L21/02343 ,  H01L21/02348 ,  H01L21/67034 ,  H01L21/67051 ,  H01L21/67173 ,  H01L21/6719 ,  H01L21/67207

Abstract: The present disclosure generally relates to apparatus and methods for forming a low-k dielectric material on a substrate. The method includes various substrate processing steps utilizing a wet processing chamber, a solvent exchange chamber, and a supercritical fluid chamber. More specifically, a dielectric material in an aqueous solution may be deposited on the substrate and a solvent exchange process may be performed to prepare the substrate for a supercritical drying process. During the supercritical drying process, liquids present in the solution and remaining on the substrate from the solvent exchange process are removed via sublimation during the supercritical drying process. The resulting dielectric material formed on the substrate may be considered a silica aerogel which exhibits a very low k-value.

公开(公告)号：US20240021582A1

公开(公告)日：2024-01-18

申请号：US18360749

申请日：2023-07-27

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/522 ,  H01L23/495 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H05K1/144 ,  H01L23/5226 ,  H01L23/49586 ,  H01L25/50

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

公开(公告)号：US20220375787A1

公开(公告)日：2022-11-24

申请号：US17323381

申请日：2021-05-18

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng LEI ,  Kurtis LESCHKIES ,  Roman GOUK ,  Giback PARK ,  Kyuil CHO ,  Tapash CHAKRABORTY ,  Han-Wen CHEN ,  Steven VERHAVERBEKE

IPC: H01L21/768 ,  H01L21/48

Abstract: The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.

公开(公告)号：US20220139884A1

公开(公告)日：2022-05-05

申请号：US17578271

申请日：2022-01-18

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/522 ,  H01L23/495 ,  H01L25/00

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

公开(公告)号：US20210159160A1

公开(公告)日：2021-05-27

申请号：US16886704

申请日：2020-05-28

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Kurtis LESCHKIES ,  Roman GOUK ,  Chintan BUCH ,  Vincent DICAPRIO ,  Bernhard STONAS ,  Jean DELMAS

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

公开(公告)号：US20190371650A1

公开(公告)日：2019-12-05

申请号：US16407510

申请日：2019-05-09

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Keith Tatseun WONG ,  Kurtis LESCHKIES ,  Namsung KIM ,  Srinivas NEMANI

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure is oxidized by a high pressure oxidation process to form a buried oxide layer adjacent the substrate.

公开(公告)号：US20150251214A1

公开(公告)日：2015-09-10

申请号：US14716489

申请日：2015-05-19

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Steven VERHAVERBEKE ,  Robert VISSER

IPC: B05D1/00 ,  D01F1/09 ,  D01D11/06 ,  B05B5/04 ,  D01D5/00

CPC classification number: B05D1/007 ,  B05B5/04 ,  B22F2009/0888 ,  B22F2009/0892 ,  B22F2202/06 ,  D01D5/0061 ,  D01D5/0092 ,  D01D11/06 ,  D01F1/09 ,  D01F6/50

Abstract: Embodiments of the invention generally include apparatus and methods for depositing nanowires in a predetermined pattern during an electrospinning process. An apparatus includes a nozzle for containing and ejecting a deposition material, and a voltage source coupled to the nozzle to eject the deposition material. One or more electric field shaping devices are positioned to shape the electric field adjacent to a substrate to control the trajectory of the ejected deposition material. The electric field shaping device converges an electric field at a point near the surface of the substrate to accurately deposit the deposition material on the substrate in a predetermined pattern. The methods include applying a voltage to a nozzle to eject an electrically-charged deposition material towards a substrate, and shaping one or more electric fields to control the trajectory of the electrically-charged deposition material. The deposition material is then deposited on the substrate in a predetermined pattern.

Abstract translation: 本发明的实施方案通常包括用于在静电纺丝过程期间以预定图案沉积纳米线的装置和方法。 一种装置包括用于容纳和喷射沉积材料的喷嘴，以及耦合到喷嘴以喷射沉积材料的电压源。 定位一个或多个电场成形装置以使与基板相邻的电场成形以控制喷出的沉积材料的轨迹。 电场成形装置在基板表面附近的点收敛电场，以预定图案将沉积材料精确地沉积在基板上。 所述方法包括向喷嘴施加电压以向基板喷射带电荷的沉积材料，以及对一个或多个电场进行整形以控制带电沉积材料的轨迹。 然后将沉积材料以预定图案沉积在基板上。