公开(公告)号：US11221798B2

公开(公告)日：2022-01-11

申请号：US16751975

申请日：2020-01-24

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.

公开(公告)号：US20200066328A1

公开(公告)日：2020-02-27

申请号：US16109720

申请日：2018-08-22

Applicant: Apple Inc.

Inventor： Peter Fu ,  Gregory S. Mathews ,  Kai Lun Hsuing ,  Shane J. Keil

IPC: G11C11/406

Abstract: A method and apparatus for performing opportunistic refreshes of memory banks is disclosed. Refresh circuitry in a memory controller performs a refresh on each bank of a multi-bank memory at least once during a given refresh interval. At the beginning of an interval, memory banks for which there are no pending transactions (e.g., reads or writes) may be refreshed. During a first portion of the interval, refresh may be skipped for memory banks for which transactions are pending. In a second portion of the interval, refreshes are performed on memory banks that have not been refreshed during the interval, which may cause some memory transactions to be delayed.

公开(公告)号：US20200004700A1

公开(公告)日：2020-01-02

申请号：US16024063

申请日：2018-06-29

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Shane J. Keil ,  Lakshmi Narasimha Nukala

IPC: G06F13/16 ,  G06F13/40 ,  G06F15/167 ,  G06F15/17

Abstract: A system and method for communication link management in a credit-based system is disclosed. In one embodiment, a system includes first and second functional circuit blocks implemented on an integrated circuit and being able to communicate with one another through establishment of source synchronous links. The first functional circuit block includes a write queue for storing data and information regarding write requests sent from the second functional circuit block. The write queue includes credit management circuitry arranged to convey one or more credits to the second functional circuit block responsive to receiving one or more write requests therefrom. Responsive to receiving the one or more credits and in the absence of any pending additional requests, the second functional circuit block may deactivate a link with the first functional circuit block.

公开(公告)号：US20170177256A1

公开(公告)日：2017-06-22

申请号：US15447328

申请日：2017-03-02

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G06F3/06 ,  G06F9/44 ,  G06F13/16 ,  G06F13/42 ,  G11C11/406 ,  G06F13/40

CPC classification number: G06F12/0223 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0673 ,  G06F9/4406 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/1032 ,  G11C11/40615 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US20150349787A1

公开(公告)日：2015-12-03

申请号：US14478387

申请日：2014-09-05

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gilbert H. Herbeck

IPC: H03L7/091 ,  H03K5/1534

CPC classification number: H03L7/091 ,  H03K5/1534

Abstract: A method and apparatus for synchronizing data transfers from a first clock domain to a second clock domain includes sampling data from circuit included in the first clock domain. The clock signal from the first clock domain may then be synchronized to a clock signal from the second clock domain. The sampled data may then be captured using the clock signal from the second clock domain responsive to a detection of an edge of the synchronized first clock signal.

Abstract translation: 用于将从第一时钟域到第二时钟域的数据传输同步的方法和装置包括从包括在第一时钟域中的电路的采样数据。 然后可以将来自第一时钟域的时钟信号与来自第二时钟域的时钟信号同步。 然后可以利用来自第二时钟域的时钟信号来捕获采样数据，以响应于同步的第一时钟信号的边沿的检测。

公开(公告)号：US09024699B2

公开(公告)日：2015-05-05

申请号：US13746247

申请日：2013-01-21

Applicant: Apple Inc.

Inventor： Kleanthes G. Koniaris ,  Erik P. Machnicki ,  Shane J. Keil

IPC: H03K3/64

CPC classification number: H03K3/64

Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

Abstract translation: 用于基于参考时钟产生输出时钟的各种技术。 本公开涉及基于参考时钟信号产生输出时钟信号。 在一个实施例中，一种方法包括：使用从控制电路接收的信息，使用输入时钟信号的第一数量的边缘或输入时钟信号和第二不同数量的边缘来产生输出时钟信号。 在本实施例中，控制电路的运行频率小于输入时钟信号的频率。 接收到的信息可以针对输出时钟信号的脉冲来指示是否应该使用第一数量的边缘或第二数量的边缘来生成脉冲。 在某些情况下，第二数量的边可以是第一数量的边加上一个边。 第一和第二数量的边缘可以是可编程的数量。

公开(公告)号：US20140203884A1

公开(公告)日：2014-07-24

申请号：US13746247

申请日：2013-01-21

Applicant: APPLE INC.

Inventor： Kleanthes G. Koniaris ,  Erik P. Machnicki ,  Shane J. Keil

IPC: H03L7/099 ,  H03K3/64

CPC classification number: H03K3/64

Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

Abstract translation: 用于基于参考时钟产生输出时钟的各种技术。 本公开涉及基于参考时钟信号产生输出时钟信号。 在一个实施例中，一种方法包括：使用从控制电路接收的信息，使用输入时钟信号的第一数量的边缘或输入时钟信号和第二不同数量的边缘来产生输出时钟信号。 在本实施例中，控制电路的运行频率小于输入时钟信号的频率。 接收到的信息可以针对输出时钟信号的脉冲来指示是否应该使用第一数量的边缘或第二数量的边缘来生成脉冲。 在某些情况下，第二数量的边可以是第一数量的边加上一个边。 第一和第二数量的边缘可以是可编程的数量。

公开(公告)号：US12216594B2

公开(公告)日：2025-02-04

申请号：US18469905

申请日：2023-09-19

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala

IPC: G06F13/16

Abstract: A memory control circuit coupled to multiple memory ranks may receive read and write requests for a different ranks of the multiple memory ranks. The memory control may allocate write requests to different slots based on the write requests target memory rank, and may adjust the number of slots available for a given memory rank during a write turn to improve write efficiency. The memory control circuit may also determine a number of ranks switches within a read turn based on whether a particular quality-of-service requirement associated with the read requests is being satisfied.

公开(公告)号：US12118249B2

公开(公告)日：2024-10-15

申请号：US18497883

申请日：2023-10-30

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Shane J. Keil ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Tao Zhang

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0644 ,  G06F3/0673 ,  G06F13/1605

Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.

公开(公告)号：US20240202146A1

公开(公告)日：2024-06-20

申请号：US18588406

申请日：2024-02-27

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Shane J. Keil

IPC: G06F13/16 ,  G06F1/06

CPC classification number: G06F13/1684 ,  G06F1/06 ,  G06F13/1647

Abstract: Techniques for scheduling memory operations are disclosed in which alternate read/write commands within a multi-bank memory operation are delayed beyond a minimum timing parameter in order to increase memory data bus utilization. The remaining read/write commands are not delayed beyond the minimum timing parameter. Every other clock cycle (e.g., even clock cycles) within the memory operation is reserved for activate commands, while other commands such as sync and read/write are scheduled on the intervening clock cycles (e.g., odd clock cycles). For memory devices for which a sync command (which causes a clock of the memory data bus to start) is to precede a corresponding read/write command by a number of clock cycles that would place it in a cycle reserved for activate commands, a particular operation mode is disclosed in which the memory device internally delays a received sync command.