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    Mechanism for reducing cache power consumption using cache way prediction
    11.
    发明授权
    Mechanism for reducing cache power consumption using cache way prediction 有权
    使用缓存方式预测降低缓存功耗的机制

    公开(公告)号：US09311098B2

    公开(公告)日：2016-04-12

    申请号：US13888551

    申请日：2013-05-07

    Applicant: Apple Inc.

    Inventor： Ronald P. Hall ,  Conrado Blasco-Allue

    IPC: G06F12/00 ,  G06F9/38 ,  G06F12/08

    CPC classification number: G06F9/3806 ,  G06F9/3838 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

    Abstract: A mechanism for reducing power consumption of a cache memory of a processor includes a processor with a cache memory that stores instruction information for one or more instruction fetch groups fetched from a system memory. The cache memory may include a number of ways that are each independently controllable. The processor also includes a way prediction unit. The way prediction unit may enable, in a next execution cycle, a given way within which instruction information corresponding to a target of a next branch instruction is stored in response to a branch taken prediction for the next branch instruction. The way prediction unit may also, in response to the branch taken prediction for the next branch instruction, enable, one at a time, each corresponding way within which instruction information corresponding to respective sequential instruction fetch groups that follow the next branch instruction are stored.

    Abstract translation: 用于降低处理器的高速缓冲存储器的功耗的机构包括具有高速缓存存储器的处理器，该高速缓冲存储器存储从系统存储器取出的一个或多个指令获取组的指令信息。 高速缓冲存储器可以包括各自独立可控的多种方式。 处理器还包括方式预测单元。 方式预测单元可以在下一个执行周期中使得响应于下一个分支指令的分支采取预测而存储对应于下一分支指令的目标的指令信息的给定方式。 方式预测单元还可以响应于对下一个分支指令的分支采取的预测，一次一个地使能存储与下一个分支指令之后的各个顺序指令获取组对应的指令信息的每个对应方式。

    Mechanism for Reducing Cache Power Consumption Using Cache Way Prediction
    12.
    发明申请
    Mechanism for Reducing Cache Power Consumption Using Cache Way Prediction 有权
    使用缓存方式预测降低高速缓存功耗的机制

    公开(公告)号：US20140337605A1

    公开(公告)日：2014-11-13

    申请号：US13888551

    申请日：2013-05-07

    Applicant: APPLE INC.

    Inventor： Ronald P. Hall ,  Conrado Blasco-Allue

    IPC: G06F9/30

    CPC classification number: G06F9/3806 ,  G06F9/3838 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

    Abstract: A mechanism for reducing power consumption of a cache memory of a processor includes a processor with a cache memory that stores instruction information for one or more instruction fetch groups fetched from a system memory. The cache memory may include a number of ways that are each independently controllable. The processor also includes a way prediction unit. The way prediction unit may enable, in a next execution cycle, a given way within which instruction information corresponding to a target of a next branch instruction is stored in response to a branch taken prediction for the next branch instruction. The way prediction unit may also, in response to the branch taken prediction for the next branch instruction, enable, one at a time, each corresponding way within which instruction information corresponding to respective sequential instruction fetch groups that follow the next branch instruction are stored.

    Abstract translation: 用于降低处理器的高速缓冲存储器的功耗的机构包括具有高速缓存存储器的处理器，该高速缓冲存储器存储从系统存储器取出的一个或多个指令获取组的指令信息。 高速缓冲存储器可以包括各自独立可控的多种方式。 处理器还包括方式预测单元。 方式预测单元可以在下一个执行周期中使得响应于下一个分支指令的分支采取预测而存储对应于下一分支指令的目标的指令信息的给定方式。 方式预测单元还可以响应于对下一个分支指令的分支采取的预测，一次一个地使能存储与下一个分支指令之后的各个顺序指令获取组对应的指令信息的每个对应方式。

    Prediction Confirmation for Cache Subsystem
    13.
    发明申请
    Prediction Confirmation for Cache Subsystem 有权

    公开(公告)号：US20230084736A1

    公开(公告)日：2023-03-16

    申请号：US17933603

    申请日：2022-09-20

    Applicant: Apple Inc.

    Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

    IPC: G06F12/0862

    Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

    Virtual Channel Support Using Write Table
    14.
    发明申请
    Virtual Channel Support Using Write Table 有权

    公开(公告)号：US20220083369A1

    公开(公告)日：2022-03-17

    申请号：US17143149

    申请日：2021-01-06

    Applicant: Apple Inc.

    Inventor： Michael D. Snyder ,  Ronald P. Hall ,  Deepak Limaye ,  Brett S. Feero ,  Rohit K. Gupta

    IPC: G06F9/46 ,  G06F9/50 ,  G06F9/54

    Abstract: An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

    Cache for patterns of instructions with multiple forward control transfers
    16.
    发明授权
    Cache for patterns of instructions with multiple forward control transfers 有权

    公开(公告)号：US09632791B2

    公开(公告)日：2017-04-25

    申请号：US14160242

    申请日：2014-01-21

    Applicant: Apple Inc.

    Inventor： Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Ronald P. Hall ,  Michael L. Karm

    IPC: G06F12/08 ,  G06F9/38 ,  G06F12/0862

    CPC classification number: G06F9/3844 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3867 ,  G06F12/0862 ,  Y02D10/13

    Abstract: Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.

    Instruction loop buffer with tiered power savings
    17.
    发明授权
    Instruction loop buffer with tiered power savings 有权
    指令循环缓冲器，具有分层功率节省

    公开(公告)号：US09524011B2

    公开(公告)日：2016-12-20

    申请号：US14251508

    申请日：2014-04-11

    Applicant: Apple Inc.

    Inventor： Ronald P. Hall ,  Michael L. Karm ,  Ian D. Kountanis ,  David J. Williamson

    IPC: G06F1/26 ,  G06F1/32 ,  G06F9/00 ,  G06F9/30

    CPC classification number: G06F1/3234 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3844

    Abstract: Techniques are disclosed relating to power reduction during execution of instruction loops. Multiple different power saving modes may be used by a processor, such as a first power saving mode after only a few loop iterations (e.g., 2-3) and a second, deeper power saving mode after a greater number of loop iterations. The first power saving mode may include keeping a branch predictor and/or other structures active, but the second power saving mode may include reducing power to the branch predictor and/or other structures. An observation mode and an instruction capture mode may also be used by a processor prior to entering a power saving mode for loop execution. Power saving modes may also be achieved during execution of complex loops having multiple backward branches (e.g., nested loops).

    Abstract translation: 公开了在执行指令循环期间降低功率的技术。 处理器可以使用多种不同的功率节省模式，例如在更多数量的循环迭代之后仅仅几次循环迭代（例如2-3）和第二更深的省电模式之后的第一省电模式。 第一省电模式可以包括保持分支预测器和/或其他结构是有效的，但是第二省电模式可以包括降低分支预测器和/或其他结构的功率。 在进入用于循环执行的省电模式之前，处理器还可以使用观察模式和指令捕获模式。 在执行具有多个后向分支（例如，嵌套循环）的复杂环路时也可以实现节电模式。

    Trace Cache with Filter for Internal Control Transfer Inclusion
    18.
    发明申请
    Trace Cache with Filter for Internal Control Transfer Inclusion 有权

    公开(公告)号：US20250021333A1

    公开(公告)日：2025-01-16

    申请号：US18352323

    申请日：2023-07-14

    Applicant: Apple Inc.

    Inventor： Ilhyun Kim ,  Niket K. Choudhary ,  Muawya M. Al-Otoom ,  Pruthivi Vuyyuru ,  Ronald P. Hall

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Disclosed techniques relate to trace caches. Trace cache circuitry may identify traces that satisfy one or more criteria. Generally, internal branches of a trace should satisfy a threshold bias level in a particular direction. To achieve this goal, the processor may initially assume that branches meet the threshold, track their usefulness in the trace context over time, and prevent inclusion of branches that fall below a usefulness threshold (which indicates that those branches are not sufficiently biased). Branches that do not meet the threshold may be added to a Bloom filter, for example. Usefulness may be tracked during trace training, when valid in a trace cache, or both.

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