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公开(公告)号：US10955893B2
公开(公告)日：2021-03-23
申请号：US16159821
申请日：2018-10-15
Applicant: Apple Inc.
Inventor： John H. Mylius , Conrad H. Ziesler , Daniel C. Murray , Jong-Suk Lee , Rohit Kumar
IPC: G06F1/32 , G06F1/3209 , G06F1/3296 , G06F1/3206 , G06F1/324 , G06F1/3287
Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.
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公开(公告)号：US20140089638A1
公开(公告)日：2014-03-27
申请号：US13627884
申请日：2012-09-26
Applicant: APPLE INC.
Inventor： John H. Mylius , Gerard R. Williams III , James B. Keller , Fang Liu , Shyam Sundar
CPC classification number: G06F9/3017 , G06F9/30138 , G06F9/3016 , G06F9/345 , G06F9/384 , G06F9/3861 , G06F9/3867
Abstract: Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline is configured to merge the plurality of single-destination operations into one or more multi-destination operations. The one or more multi-destination operations may be performed. The first portion of the pipeline may include a decode unit. The second portion of the pipeline may include a map unit, which may in turn include circuitry configured to maintain a list of free architectural registers and a mapping table that maps physical registers to architectural registers. The third portion of the pipeline may comprise a dispatch unit. In some embodiments, this may provide certain advantages such as reduced area and/or power consumption.
Abstract translation: 用于处理指定多个目的地的指令的各种技术。 处理器流水线的第一部分被配置为将多目的地指令分割成多个单目的地操作。 流水线的第二部分被配置为处理多个单目的地操作。 流水线的第三部分被配置为将多个单目的地操作合并成一个或多个多目的地操作。 可以执行一个或多个多目的地操作。 流水线的第一部分可以包括解码单元。 流水线的第二部分可以包括地图单元，其可以依次包括被配置为维护空闲架构寄存器的列表的电路和将物理寄存器映射到架构寄存器的映射表。 管道的第三部分可以包括调度单元。 在一些实施例中，这可以提供某些优点，例如减小面积和/或功率消耗。
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公开(公告)号：US20130132781A1
公开(公告)日：2013-05-23
申请号：US13741436
申请日：2013-01-15
Applicant: Apple Inc.
Inventor： Kevin R. Walker , John H. Mylius
IPC: G06F11/36
CPC classification number: G06F11/3636 , G06F11/3476
Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.
Abstract translation: 在一个实施例中，集成电路包括被配置为输出程序计数器（PC）跟踪记录的第一处理器，其中PC跟踪记录提供指示由第一处理器退休的指令的PC的数据。 集成电路还包括跟踪记录的第二源，以及耦合以从第一处理器接收PC跟踪记录和来自第二源的跟踪记录的跟踪单元。 跟踪单元包括跟踪单元，跟踪单元被配置为存储来自第二个源的PC跟踪记录和跟踪记录。 跟踪单元被配置为根据记录的接收顺序将跟踪记录和跟踪记录中的跟踪记录交错在跟踪存储器中。
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公开(公告)号：US12235703B2
公开(公告)日：2025-02-25
申请号：US18351248
申请日：2023-07-12
Applicant: Apple Inc.
Inventor： John H. Mylius , Conrad H. Ziesler , Daniel C. Murray , Jong-Suk Lee , Rohit Kumar
IPC: G06F1/00 , G06F1/32 , G06F1/3206 , G06F1/3209 , G06F1/324 , G06F1/3287 , G06F1/3296
Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances.
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公开(公告)号：US20210173465A1
公开(公告)日：2021-06-10
申请号：US17177521
申请日：2021-02-17
Applicant: Apple Inc.
Inventor： John H. Mylius , Conrad H. Ziesler , Daniel C. Murray , Jong-Suk Lee , Rohit Kumar
IPC: G06F1/3209 , G06F1/3206 , G06F1/3296 , G06F1/324 , G06F1/3287
Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.
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Patent Agency Ranking
公开(公告)号：US20170160791A1
公开(公告)日：2017-06-08
申请号：US15433201
申请日：2017-02-15
Applicant: Apple Inc.
Inventor： John H. Mylius , Conrad H. Ziesler , Daniel C. Murray , Jong-Suk Lee , Rohit Kumar
IPC: G06F1/32
CPC classification number: G06F1/3209 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.
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17.发明授权公开(公告)号：US09535695B2
公开(公告)日：2017-01-03
申请号：US13750942
申请日：2013-01-25
Applicant: Apple Inc.
Inventor： John H. Mylius , Rajat Goel , Pradeep Kanapathipillai , Hari S. Kannan
CPC classification number: G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855
Abstract: Techniques are disclosed relating to completion of load and store instructions in a weakly-ordered memory model. In one embodiment, a processor includes a load queue and a store queue and is configured to associate queue information with a load instruction in an instruction stream. In this embodiment, the queue information indicates a location of the load instruction in the load queue and one or more locations in the store queue that are associated with one or more store instructions that are older than the load instruction. The processor may determine, using the queue information, that the load instruction does not conflict with a store instruction in the store queue that is older than the load instruction. The processor may remove the load instruction from the load queue while the store instruction remains in the store queue. The queue information may include a wrap value for the load queue.
Abstract translation: 公开了在弱有序存储器模型中完成负载和存储指令的技术。 在一个实施例中，处理器包括加载队列和存储队列，并且被配置为将队列信息与指令流中的加载指令相关联。 在该实施例中，队列信息指示加载队列中的加载指令的位置和存储队列中与一个或多个比加载指令更早的存储指令相关联的一个或多个位置。 处理器可以使用队列信息来确定加载指令不与存储队列中比加载指令更早的存储指令冲突。 当存储指令保留在存储队列中时，处理器可以从加载队列中移除加载指令。 队列信息可以包括加载队列的换行值。
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18.发明授权公开(公告)号：US09223577B2
公开(公告)日：2015-12-29
申请号：US13627884
申请日：2012-09-26
Applicant: Apple Inc.
Inventor： John H. Mylius , Gerard R. Williams, III , James B. Keller , Fang Liu , Shyam Sundar
CPC classification number: G06F9/3017 , G06F9/30138 , G06F9/3016 , G06F9/345 , G06F9/384 , G06F9/3861 , G06F9/3867
Abstract: Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline is configured to merge the plurality of single-destination operations into one or more multi-destination operations. The one or more multi-destination operations may be performed. The first portion of the pipeline may include a decode unit. The second portion of the pipeline may include a map unit, which may in turn include circuitry configured to maintain a list of free architectural registers and a mapping table that maps physical registers to architectural registers. The third portion of the pipeline may comprise a dispatch unit. In some embodiments, this may provide certain advantages such as reduced area and/or power consumption.
Abstract translation: 用于处理指定多个目的地的指令的各种技术。 处理器流水线的第一部分被配置为将多目的地指令分割成多个单目的地操作。 流水线的第二部分被配置为处理多个单目的地操作。 流水线的第三部分被配置为将多个单目的地操作合并成一个或多个多目的地操作。 可以执行一个或多个多目的地操作。 流水线的第一部分可以包括解码单元。 流水线的第二部分可以包括地图单元，其可以依次包括被配置为维护空闲架构寄存器的列表的电路和将物理寄存器映射到架构寄存器的映射表。 管道的第三部分可以包括调度单元。 在一些实施例中，这可以提供某些优点，例如减小面积和/或功率消耗。
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公开(公告)号：US20230122955A1
公开(公告)日：2023-04-20
申请号：US17821394
申请日：2022-08-22
Applicant: Apple Inc.
Inventor： John H. Mylius , Conrad H. Ziesler , Daniel C. Murray , Jong-Suk Lee , Rohit Kumar
IPC: G06F1/3209 , G06F1/3296 , G06F1/3206 , G06F1/324 , G06F1/3287
Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g., to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.
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公开(公告)号：US20190050043A1
公开(公告)日：2019-02-14
申请号：US16159821
申请日：2018-10-15
Applicant: Apple Inc.
Inventor： John H. Mylius , Conrad H. Ziesler , Daniel C. Murray , Jong-Suk Lee , Rohit Kumar
IPC: G06F1/32
Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.
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