公开(公告)号：US20130132781A1

公开(公告)日：2013-05-23

申请号：US13741436

申请日：2013-01-15

Applicant: Apple Inc.

Inventor： Kevin R. Walker ,  John H. Mylius

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3476

Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

Abstract translation: 在一个实施例中，集成电路包括被配置为输出程序计数器（PC）跟踪记录的第一处理器，其中PC跟踪记录提供指示由第一处理器退休的指令的PC的数据。 集成电路还包括跟踪记录的第二源，以及耦合以从第一处理器接收PC跟踪记录和来自第二源的跟踪记录的跟踪单元。 跟踪单元包括跟踪单元，跟踪单元被配置为存储来自第二个源的PC跟踪记录和跟踪记录。 跟踪单元被配置为根据记录的接收顺序将跟踪记录和跟踪记录中的跟踪记录交错在跟踪存储器中。

公开(公告)号：US20130159775A1

公开(公告)日：2013-06-20

申请号：US13765920

申请日：2013-02-13

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Kevin R. Walker ,  Mitchell P. Lichtenberg

IPC: G06F11/26

CPC classification number: G06F11/26 ,  G06F11/3656

Abstract: A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

Abstract translation: 公开了一种停止用于调试目的的集成电路（IC）的功能块的方法和装置。 在一个实施例中，IC包括可由外部调试器经由调试端口（DP）访问的多个功能单元。 在调试操作期间，IC中的电源控制器可以关闭功能单元。 当功能单元关闭电源时，可以对第一个寄存器进行编程。 响应于第一寄存器的编程，第一信号可以被断言并提供给功能单元。 当功能恢复到功能单元时，可以在执行指令或其他操作之前响应于该信号来停止功能单元的操作。

公开(公告)号：US08694830B2

公开(公告)日：2014-04-08

申请号：US13765920

申请日：2013-02-13

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Kevin R. Walker ,  Mitchell P. Lichtenberg

IPC: G06F11/00

CPC classification number: G06F11/26 ,  G06F11/3656

Abstract: A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

Abstract translation: 公开了一种停止用于调试目的的集成电路（IC）的功能块的方法和装置。 在一个实施例中，IC包括可由外部调试器经由调试端口（DP）访问的多个功能单元。 在调试操作期间，IC中的电源控制器可以关闭功能单元。 当功能单元关闭电源时，可以对第一个寄存器进行编程。 响应于第一寄存器的编程，第一信号可以被断言并提供给功能单元。 当功能恢复到功能单元时，可以在执行指令或其他操作之前响应于该信号来停止功能单元的操作。

公开(公告)号：US08583967B2

公开(公告)日：2013-11-12

申请号：US13741436

申请日：2013-01-15

Applicant: Apple Inc.

Inventor： Kevin R. Walker ,  John H. Mylius

IPC: G06F11/00

CPC classification number: G06F11/3636 ,  G06F11/3476

Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.