公开(公告)号：US3983497A

公开(公告)日：1976-09-28

申请号：US557040

申请日：1975-03-10

申请人： Wilhelm Hegeler

发明人： Wilhelm Hegeler

IPC分类号： G01R23/00 ,  H03D3/24 ,  H03L7/099 ,  H03B3/04

CPC分类号： H03D3/24 ,  G01R23/00 ,  H03L7/0992

摘要： A signal frequency, controlled by the output of a phase comparator, is obtained from a constant or reference signal frequency source by means of a frequency divider, the division ratio of which is voltage-controlled and variable, the control signal being obtained from the output of the phase comparator, in digital, or analog form. When in analog form, a monostable multivibrator is interposed so that a voltage-controlled divider having a division ratio of an average, predetermined factor can be used. The signal, the frequency of which is to be identified, is applied as one input to the phase comparator for comparison with the output signal from the frequency divider, the comparison providing the aforementioned division control signal.

摘要翻译： 由相位比较器的输出控制的信号频率通过分频器从恒定或参考信号频率源获得，分频比是电压控制和可变的，控制信号从输出端获得 的相位比较器，以数字或模拟形式。 当以模拟形式插入单稳态多谐振荡器时，可以使用具有平均值，预定因子的分压比的电压控制分压器。 将要识别的频率的信号作为一个输入施加到相位比较器，以与来自分频器的输出信号进行比较，比较提供前述的分频控制信号。

公开(公告)号：US3949401A

公开(公告)日：1976-04-06

申请号：US551689

申请日：1975-02-21

申请人： Wilhelm Hegeler ,  Lambert Maschmeyer ,  Hans Rasehorn

发明人： Wilhelm Hegeler ,  Lambert Maschmeyer ,  Hans Rasehorn

IPC分类号： G08G1/09 ,  H04B7/00

CPC分类号： G08G1/094

摘要： Frequencies which respectively identify a particular transmitter, and a particular program content, and which are in a very low frequency range (from between 20 to 125 kHz can be recognized, and ditigal output control signals derived representative of whether one, or both, or none of these frequencies are present by use of a frequency selection input circuit, controlled by a change-over switch to initially select recognition of the transmitter identification which, if positive, is applied through a storage circuit having a storage time substantially longer than the switch-over rate, to provide an output signal if the selected transmitter is recognized, and hold that output signal during switch-over of the program content identification signal which, if present, will be fed back through a logic circuit to hold the output of the transmitter identification circuit as identified, and if not present, permit continued switch-over of the frequency identification circuit to continue to store transmitter identification signals, if present, but permit these signals to disappear, after the storage time, if the transmitter identification signals also cease. The time delay and storage circuit preferably include operational amplifiers, and the frequency identification circuit includes a phase-locked loop.

摘要翻译： 可以识别分别识别特定发射机和特定节目内容并且处于非常低的频率范围（从20到125kHz之间的频率）的频率以及代表一个或两个或者两者的二进制输出控制信号 这些频率通过使用频率选择输入电路存在，由转换开关控制，以最初选择识别发射机标识，发射机标识如果通过具有比开关转换器的存储时间大得多的存储电路被施加， 如果所选择的发射机被识别，则提供输出信号，并且在节目内容识别信号的切换期间保持该输出信号，如果存在的话，将通过逻辑电路反馈以保持发射机的输出 识别电路，如果不存在，允许频率识别电路继续切换以继续存储t 发射机识别信号，如果存在，但允许这些信号消失，在存储时间之后，如果发射机识别信号也停止。 时间延迟和存储电路优选地包括运算放大器，并且频率识别电路包括锁相环。

公开(公告)号：US06195783B1

公开(公告)日：2001-02-27

申请号：US08913371

申请日：1997-09-19

申请人： Detlev Nyenhuis ,  Wilhelm Hegeler

发明人： Detlev Nyenhuis ,  Wilhelm Hegeler

IPC分类号： G06F1100

CPC分类号： H04H40/18 ,  H04H2201/13 ,  H04L7/048

摘要： A process and apparatus for synchronizing the block counter of an RDS radio data receiver is described. According to the process, the bits stored in a 26-bit shift register, are cycled at least n times in said register, n being the number of allowable offset words, and the shift register content is X-OR gated with another offset word in a given sequence for each cycle. The gating result is received by a syndrome detection circuit, which triggers a sync pulse when the zero syndrome is detected, and the sync pulse resets the bit counter to zero and sets the block counter to the address counter status assigned to the offset word in the offset word generator.

摘要翻译： 描述了用于同步RDS无线电数据接收机的块计数器的过程和装置。 根据该处理，存储在26位移位寄存器中的位在所述寄存器中至少循环n次，n是可允许偏移字的数量，并且移位寄存器内容是与另一个偏移量的X-OR门控 每个周期的给定序列。 门诊结果由检测到零零点检测电路触发同步脉冲的异常检测电路接收，同步脉冲将位计数器复位为零，并将块计数器设置为分配给偏移字的地址计数器状态 偏移字生成器。

公开(公告)号：US5278560A

公开(公告)日：1994-01-11

申请号：US818058

申请日：1992-01-08

申请人： Wilhelm Hegeler ,  Jurgen Kasser

发明人： Wilhelm Hegeler ,  Jurgen Kasser

IPC分类号： H03K5/1536 ,  H03K5/08 ,  H03M1/44

CPC分类号： H03K5/086

摘要： In a circuit arrangement for deriving a binary signal from an alternating voltage (U), in which the alternating voltage can be delivered via a capacitor to the input of a threshold value circuit and a reference voltage obtained by integration serves to adjust the operating point at the input, an up/down counter is provided for deriving the reference voltage, its counting direction being controllable by the binary signal. From the output signal of the up/down counter, a further binary signal is derived, which after integration forms the reference voltage. The circuit is suitable for use in evaluating the data subcarrier component of a Radio Data System (RDS) signal, as defined by European Broadcasting Union (EBU) Technical Standard 3244-E.

摘要翻译： 在用于从交流电压（U）导出二进制信号的电路装置中，其中可以经由电容器将交流电压输送到阈值电路的输入，并且通过积分获得的参考电压用于调整工作点在 输入，提供用于导出参考电压的向上/向下计数器，其计数方向由二进制信号控制。 从上/下计数器的输出信号，导出另外的二进制信号，其在积分后形成参考电压。 该电路适用于评估由欧洲广播联盟（EBU）技术标准3244-E定义的无线电数据系统（RDS）信号的数据子载波分量。

公开(公告)号：US4727331A

公开(公告)日：1988-02-23

申请号：US18842

申请日：1987-02-24

申请人： Wilhelm Hegeler

发明人： Wilhelm Hegeler

IPC分类号： B06B1/02 ,  G08G1/09 ,  H03K3/017 ,  H03K3/64 ,  H03K3/01 ,  H03K5/22

CPC分类号： H03K3/64 ,  B06B1/0276 ,  H03K3/017

摘要： Pulses of constant pulse frequency but varying duty cycle are generated in a pulse generator which provides pulse trains or pulse sequences, as controlled by a pulse train or pulse length or sequence control unit coupled to the pulse generator and controlling the pulse generator to emit a train or sequence of pulses of similar pulse lengths, and further including a pulse length modulation control unit (12) coupled to the pulse generator and to the pulse train or sequence control unit, to control the length of the pulses of the individual pulse trains, the pulse lengths increasing in sequential pulse trains to provide an output signal of increasing intensity. The output from the pulse generator is filtered with respect to the base frequency, for example 800 Hz, and generated square wave pulses are converted into sawtooth wave pulses by a RC circuit to increase the dynamic range of output obtainable. The pulse generator (10), the pulse train length control unit (11) and the pulse length modulation control unit (12) can all form part of a digital microprocessor, generating the pulses, with intervening intervals to provide for a warning tone rhythm, the intervening intervals permitting the microprocessor to carry out calculating functions other than pulse generation for the warning tone.

摘要翻译： 在脉冲发生器中产生恒定脉冲频率但变化的占空比的脉冲，该脉冲发生器提供脉冲串或脉冲序列，由脉冲串或脉冲长度或序列控制单元控制，脉冲序列或序列控制单元耦合到脉冲发生器并控制脉冲发生器发射列车 或类似脉冲长度的脉冲序列，并且还包括耦合到脉冲发生器和脉冲串或序列控制单元的脉冲长度调制控制单元（12），以控制单个脉冲序列的脉冲长度， 在脉冲序列中脉冲长度增加，以提供强度增加的输出信号。 来自脉冲发生器的输出相对于基频（例如800Hz）被滤波，并且通过RC电路将生成的方波脉冲转换成锯齿波脉冲以增加可获得的输出的动态范围。 脉冲发生器（10），脉冲串长度控制单元（11）和脉冲长度调制控制单元（12）都可以形成数字微处理器的一部分，以间隔的间隔产生脉冲以提供警告音节奏， 中间间隔允许微处理器执行用于警告音的脉冲生成以外的计算功能。