公开(公告)号：US5463746A

公开(公告)日：1995-10-31

申请号：US968790

申请日：1992-10-30

申请人： Timothy B. Brodnax ,  Bryan K. Bullis ,  Steven A. King ,  Peter M. Kogge ,  Dale A. Rickard

发明人： Timothy B. Brodnax ,  Bryan K. Bullis ,  Steven A. King ,  Peter M. Kogge ,  Dale A. Rickard

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30178 ,  G06F9/30 ,  G06F9/3844

摘要： A data processing system includes branch prediction apparatus for storing branch data in a branch prediction RAM after each branch has occurred. The RAM interfaces with branch logic means which tracks whether a branch is in progress and if a branch was guessed. An operational code compression means forms each instruction into a new operation code of lesser bits and embeds a guess bit into the new operational code. Control means decode the compressed operational code as an input to an instruction execution unit whereby conditional branch occurs based on the guess bit provided a branch instruction is not in progress in the system.

摘要翻译： 数据处理系统包括分支预测装置，用于在每个分支发生之后在分支预测RAM中存储分支数据。 RAM与分支逻辑装置接口，跟踪分支是否正在进行，如果分支被猜测。 操作代码压缩装置将每个指令形成为较小位的新操作代码，并将猜测位嵌入到新的操作代码中。 控制装置将压缩的操作码解码为指令执行单元的输入，从而基于所提供的猜测位发生条件分支，系统中未进行分支指令。

公开(公告)号：US4370732A

公开(公告)日：1983-01-25

申请号：US187256

申请日：1980-09-15

申请人： Peter M. Kogge

发明人： Peter M. Kogge

IPC分类号： G06F9/345 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06 ,  G06F17/16 ,  G06F9/34

CPC分类号： G06F9/3552 ,  G06F12/0207 ,  G06F9/345

摘要： An address generator for an M-interleaved memory for accessing row or column elements of a matrix stored in a skewed matrix pattern includes an apparatus for circularly shifting the addresses for the i.sup.th row of a matrix by s(i-1) positions so that both row and column elements of the matrix can be accessed at the same access rate. In other words, apparatus is provided for circularly generating the sequences of appropriate memory addresses for the desired row or column elements so that either the row or column elements can be accessed at the memory system's maximum access rate. The apparatus includes a base register having an input connected to a first adder which adds an input value A to the contents in the base register for storing the output of the adder as a pointer to the beginning of the current row of the matrix in the memory to be accessed. The apparatus further includes an index register having an input connected to an adder for adding an input value B to the contents of the index register and that sum is conditionally added in a third adder to an input value C which sum is then stored in the index register for indicating which column element in the matrix is to be accessed. The apparatus further includes an adder having inputs connected to the base register and the index register for generating the skewed matrix address to be accessed. The resulting apparatus enables both row and column elements of the matrix to be accessed at substantially the same rate.

摘要翻译： 用于访问存储在偏斜矩阵模式中的矩阵的行或列元素的M交错存储器的地址生成器包括用于将矩阵的第i行的地址循环移位s（i-1）位置的装置， 可以以相同的访问速率访问矩阵的行和列元素。 换句话说，提供了用于循环地产生用于所需行或列元素的适当存储器地址的序列的装置，使得可以以存储器系统的最大访问速率访问行或列元素。 该装置包括基本寄存器，其具有连接到第一加法器的输入端，该第一加法器将输入值A与基址寄存器中的内容相加，用于存储加法器的输出作为指向存储器中矩阵的当前行的开头的指针 被访问。 该装置还包括索引寄存器，该索引寄存器具有连接到加法器的输入端，用于将输入值B加到索引寄存器的内容，并且该和被有条件地相加于第三加法器中的输入值C，该输入值C将该和存储在索引中 用于指示矩阵中哪个列元素被访问的寄存器。 该装置还包括加法器，其具有连接到基址寄存器和索引寄存器的输入端，用于产生要访问的偏斜矩阵地址。 所得到的装置能够以基本上相同的速率访问矩阵的行和列元素。

公开(公告)号：US20130044588A1

公开(公告)日：2013-02-21

申请号：US13585410

申请日：2012-08-14

申请人： Peter M. Kogge

发明人： Peter M. Kogge

IPC分类号： H04L12/28 ,  H04L29/14

CPC分类号： H04L12/42 ,  H04L45/02 ,  H04L45/06 ,  H04L45/48

摘要： A topology for routing message traffic between interconnecting nodes of a network is provided that includes a plurality of rings having a plurality of interconnecting nodes. A number of trees include at least one leaf at a same relative position of the rings. The trees and the rings form a unique combination that provides superior network performance for moderate numbers of the interconnecting nodes, wherein each interconnecting node has only a limited ability to handle a plurality of links.

摘要翻译： 提供了一种用于在网络的互连节点之间路由消息业务的拓扑，其包括具有多个互连节点的多个环。 许多树包括在环的相同相对位置处的至少一个叶。 树和环形成独特的组合，其为中等数量的互连节点提供优异的网络性能，其中每个互连节点仅具有处理多个链路的有限能力。

公开(公告)号：US5615360A

公开(公告)日：1997-03-25

申请号：US310005

申请日：1994-09-21

申请人： John D. Bezek ,  Peter M. Kogge

发明人： John D. Bezek ,  Peter M. Kogge

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F17/30 ,  G06F12/00

CPC分类号： G06F15/17368 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F7/483 ,  F02B2075/027 ,  Y10S707/99936

摘要： The computer system has its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior ad performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions. The computer system is provided with a language construct which is language independent in the form of a sub-set paradigm having three basic operators and three basic extensions. The basic primitive sub-set paradigm including OUT(); IN() and READ(). Extensions of said basic sub-set are Sample(); SampleList(); and ReadList(). These primitives may be used with LINDA, and with various compilers. EVAL of LINDA is not used but instead the sub-set paradigm is used with CAM for tuple space operations in data base applications. The language construct paradigm is use to envelope and control CAM operations.

摘要翻译： 计算机系统具有并行和串行实现，其串行和并行网络和多处理器配置，处理器之间具有紧密和松散的耦合。 计算机系统具有耦合到计算机系统或嵌入其中的CAM。 CAM请求可以串行处理，也可以作为并行查询，并与PAPS（并行关联处理器系统）功能（P-CAM）相结合。 计算机系统可以被配置为优选地具有组合元组空间（TS）和CAM（内容可寻址存储器）资源，推理机和知识库的专家系统。 作为一个专家系统，提供了生产处理方面的改进，超越了RETE和CLIPS所代表的先前的广告效果。 公开了生产系统的推理过程，以及用于处理存储器元件断言的过程。 计算机系统具有语言独立的语言结构，其具有具有三个基本操作符和三个基本扩展的子集范例的形式。 包括OUT（）的基本原语子集范例; IN（）和READ（）。 所述基本子集的扩展是Sample（）; SampleList（）; 和ReadList（）。 这些原语可以与LINDA和各种编译器一起使用。 不使用LINDA的EVAL，而是使用子集范例与CAM一起用于数据库应用程序中的元组空间操作。 语言构建范例用于包络和控制CAM操作。

公开(公告)号：US5615309A

公开(公告)日：1997-03-25

申请号：US356925

申请日：1994-12-14

申请人： John D. Bezek ,  Peter M. Kogge

发明人： John D. Bezek ,  Peter M. Kogge

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06N5/04 ,  G06F15/18

CPC分类号： G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F7/483 ,  G06N5/046 ,  F02B2075/027 ,  Y10S707/99933

摘要： A computer system, and its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior art performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions. The computer system is provided with a language construct which is language independent in the form of a sub-set paradigm having three basic operators and three basic extensions. The basic primitive sub-set paradigm including OUT(); IN() and READ(). Extensions of said basic sub-set are Sample(); SampleList(); and ReadList(). These primitives may be used with LINDA, and with various compilers. EVAL of LINDA is not used but instead the sub-set paradigm is used with CAM for tuple space operations in data base applications. The language construct paradigm is use to envelope and control CAM operations.

摘要翻译： 计算机系统及其并行和串行实现，其串行和并行网络和多处理器配置，处理器之间的紧耦合和松散耦合。 计算机系统具有耦合到计算机系统或嵌入其中的CAM。 CAM请求可以串行处理，也可以作为并行查询，并与PAPS（并行关联处理器系统）功能（P-CAM）相结合。 计算机系统可以被配置为优选地具有组合元组空间（TS）和CAM（内容可寻址存储器）资源，推理机和知识库的专家系统。 作为专家系统，提供了超越RETE和CLIPS代表的现有技术性能的生产处理方面的改进。 公开了生产系统的推理过程，以及用于处理存储器元件断言的过程。 计算机系统具有语言独立的语言结构，其具有具有三个基本操作符和三个基本扩展的子集范例的形式。 包括OUT（）的基本原语子集范例; IN（）和READ（）。 所述基本子集的扩展是Sample（）; SampleList（）; 和ReadList（）。 这些原语可以与LINDA和各种编译器一起使用。 不使用LINDA的EVAL，而是使用子集范例与CAM一起用于数据库应用程序中的元组空间操作。 语言构建范例用于包络和控制CAM操作。

公开(公告)号：US5608448A

公开(公告)日：1997-03-04

申请号：US419474

申请日：1995-04-10

申请人： Vincent J. Smoral ,  Peter M. Kogge ,  Phillip J. Sementilli, Jr.

发明人： Vincent J. Smoral ,  Peter M. Kogge ,  Phillip J. Sementilli, Jr.

IPC分类号： H04L12/56 ,  H04N7/173 ,  H04N21/21 ,  H04N21/23 ,  H04Q11/04 ,  H04N7/10

CPC分类号： H04N21/21 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/3081 ,  H04N21/23 ,  H04N7/17336 ,  H04Q11/0478 ,  H04L2012/561 ,  H04L2012/5642

摘要： Processing requirement at each computing element in a video server for a video on demand (VOD) system are reduced to only those needed for VOD, resulting in a less expensive processor with less memory and, hence, lower cost. A hybrid video server architecture combines the best features of massive parallel processor (MPP) and workstation designs into a cost effective high performance system. Since it is not necessary to run a parallel relational database program in order to accomplish VOD data distribution, a unique type of switch element that is well matched to the VOD server problem is employed. By matching this switch element technology to an appropriate data storage technique, a full featured, responsive VOD server is realized that can be affordably installed at regional cable distribution centers nationwide.

摘要翻译： 用于视频点播（VOD）系统的视频服务器中的每个计算元件的处理要求仅减少到VOD所需的处理要求，导致较便宜的处理器，具有较少的存储器，并因此降低成本。 混合视频服务器架构将大规模并行处理器（MPP）和工作站设计的最佳功能结合成一个具有成本效益的高性能系统。 由于不需要运行并行关系数据库程序来完成VOD数据分发，所以采用与VOD服务器问题很好匹配的独特类型的交换单元。 通过将这种开关元件技术与适当的数据存储技术相结合，实现了一个功能全面的响应式VOD服务器，可以经济地安装在全国的区域电缆分销中心。

公开(公告)号：US5590345A

公开(公告)日：1996-12-31

申请号：US887630

申请日：1992-05-22

申请人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald G. Grice ,  Peter M. Kogge ,  David C. Kuchinski ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Miles ,  Richard E. Nier ,  Eric E. Retter ,  Robert R. Richardson ,  David B. Rolfe ,  Nicholas J. Schoonover ,  Vincent J. Smoral ,  James R. Stupp ,  Paul A. Wilkinson

发明人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald G. Grice ,  Peter M. Kogge ,  David C. Kuchinski ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Miles ,  Richard E. Nier ,  Eric E. Retter ,  Robert R. Richardson ,  David B. Rolfe ,  Nicholas J. Schoonover ,  Vincent J. Smoral ,  James R. Stupp ,  Paul A. Wilkinson

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F7/483 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F15/8092 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  G06F9/3891 ,  F02B2075/027

摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

摘要翻译： 一种具有多个处理器和存储器的计算机系统，所述存储器包括具有多个相似处理器存储器元件的多个可伸缩节点。 每个处理器存储器元件具有用于在节点内与节点内的其它类似处理器存储器元件通信的多个通信路径。 每个处理器存储器元件还具有用于将节点外部通信到另一个类似计算机系统的可伸缩节点的通信路径。

公开(公告)号：US4912707A

公开(公告)日：1990-03-27

申请号：US235345

申请日：1988-08-23

申请人： Peter M. Kogge ,  Khoan T. Truong ,  Dale A. Rickard ,  Robert L. Schoenike

发明人： Peter M. Kogge ,  Khoan T. Truong ,  Dale A. Rickard ,  Robert L. Schoenike

IPC分类号： G06F9/38 ,  G06F11/14

CPC分类号： G06F11/141 ,  G06F9/3863

摘要： An improved checkpoint retry mechanism is disclosed which automatically updates checkpoint addresses to enable the retry of instruction sequences for shorter segments of recently executed code, in response to the detection of an error since the passage of the current checkpoint. It does this by updating three different types of checkpoint addresses, a first checkpoint address for the instruction which follows a memory write or I/O write operation, a second type checkpoint address for the first instruction in an interrupt service routine, and a third type checkpoint address for the first instruction in an interrupted routine following an interrupt event. The resulting checkpoint retry mechanism is more efficient and faster because it adaptively updates the checkpoint address to reduce the size of code segments which must be reexecuted during retry operations. The invention operates to avoid memory corruption and erroneous I/O outputs during retry operations and protects from erroneous retry sequences.