公开(公告)号：US20110122711A1

公开(公告)日：2011-05-26

申请号：US12904302

申请日：2010-10-14

申请人： Ki-Heung KIM ,  Seong-Jin JANG ,  Myeong-O KIM ,  Hong-Jun LEE ,  Tae-Yoon LEE

发明人： Ki-Heung KIM ,  Seong-Jin JANG ,  Myeong-O KIM ,  Hong-Jun LEE ,  Tae-Yoon LEE

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/1204

摘要： A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to place a bitline precharge voltage at an edge of a dead zone. The bitline precharge voltage providing unit provides the bitline precharge voltage to the output node, and sets the bitline precharge voltage to a target level. The bitline precharge voltage generator generates the bitline precharge voltage having a distribution including the dead zone.

摘要翻译： 位线预充电电压发生器包括泄漏修整单元和位线预充电电压提供单元。 泄漏修整单元向输出节点施加泄漏电流以将位线预充电电压置于死区的边缘。 位线预充电电压提供单元向输出节点提供位线预充电电压，并将位线预充电电压设置为目标电平。 位线预充电电压发生器产生具有包括死区的分布的位线预充电电压。

公开(公告)号：US20090040853A1

公开(公告)日：2009-02-12

申请号：US12187269

申请日：2008-08-06

申请人： Myeong-O KIM ,  Byung-Chul KIM ,  Yong-Gyu CHU

发明人： Myeong-O KIM ,  Byung-Chul KIM ,  Yong-Gyu CHU

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1048 ,  G11C7/12 ,  G11C8/18

摘要： A method and semiconductor memory device for precharging a local input/output line. The semiconductor memory device, which may have an open bit line structure, transmits data through local input/output lines that are coupled to bit lines of first to n-th memory cell array blocks (n being a natural number). The semiconductor memory device may include a precharge unit configured to generate a plurality of precharge signals and a controller configured to control precharging of the at least one local input/output line responsive to block information corresponding to activation of at least one of the memory cell array blocks and responsive to at least one of the precharge signals.

摘要翻译： 一种用于对本地输入/输出线进行预充电的方法和半导体存储器件。 可以具有开放位线结构的半导体存储器件通过耦合到第一至第n存储器单元阵列块（n为自然数）的位线的本地输入/输出线传输数据。 半导体存储器件可以包括：预充电单元，其被配置为产生多个预充电信号;以及控制器，被配置为响应于对应于至少一个存储单元阵列的激活来控制至少一个本地输入/输出线的预充电 并且响应于至少一个预充电信号。

公开(公告)号：US07643364B2

公开(公告)日：2010-01-05

申请号：US12004291

申请日：2007-12-20

申请人： Jong-Cheol Lee ,  Myeong-O Kim

发明人： Jong-Cheol Lee ,  Myeong-O Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096

摘要： A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level is disclosed. The semiconductor memory device includes a sense amplification enable signal control portion which receives an initial sense amplification enable signal, sequentially delays the initial sense amplification enable signal by a plurality of predetermined time periods and selectively outputs a plurality of delayed sense amplification enable signals in view of both an operation speed and a manufacturing yield of a semiconductor memory device; a plurality of clocked sense amplifiers which each receive an output signal of the I/O sense amplifier, amplify the output signal of the I/O sense amplifier in response to each of the plurality of delayed sense amplification enable signals, and sequentially output an output signal of a power voltage level or a ground voltage level in response; and a previous-step output driving circuit which sequentially receives the output signals of the plurality of clocked sense amplifiers, delays the output signals of the plurality of clocked sense amplifiers by a predetermined time period, and then intercepts an output of the clocked sense amplifier of a previous step.

摘要翻译： 一种半导体存储器件，包括位线读出放大器，用于放大与存储在存储单元的电容器中的电荷相对应的电压并输出放大电压;以及I / O读出放大器，用于接收位线读出放大器的输出，放大 公开了输出的电压电平并输出放大的电压电平。 半导体存储器件包括读出放大使能信号控制部分，其接收初始读出放大使能信号，将初始读出放大使能信号顺序地延迟多个预定时间周期，并且选择性地输出多个延迟读出放大使能信号， 半导体存储器件的操作速度和制造成品率; 多个时钟读出放大器，其各自接收I / O读出放大器的输出信号，响应于多个延迟读出放大使能信号中的每一个放大I / O读出放大器的输出信号，并依次输出输出 电源电压信号或接地电压电平响应; 以及前级输出驱动电路，其依次接收多个时钟读出放大器的输出信号，将多个时钟读出放大器的输出信号延迟预定的时间周期，然后截取时钟感测放大器的输出 前一步。

公开(公告)号：US06879533B2

公开(公告)日：2005-04-12

申请号：US10609071

申请日：2003-06-27

申请人： Moo-sung Chae ,  Myeong-o Kim ,  Sung-min Seo

发明人： Moo-sung Chae ,  Myeong-o Kim ,  Sung-min Seo

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

摘要： An integrated circuit memory device can include a memory cell array having a plurality of memory cells, and a bit line sense amplifier configured to amplify data on a pair of bit lines from a memory cell of the memory cell array and to provide the amplified data on a data line and a complementary data line. An active load circuit includes a first load device electrically connected between the data line and a voltage source wherein an electrical resistance of the first load device is varied responsive to a voltage level of the data line. The active load circuit also includes a second load device electrically connected between the complementary data line and the voltage source wherein an electrical resistance of the second load device is varied responsive to a voltage level of the complementary data line. Related methods are also discussed.

摘要翻译： 集成电路存储器件可以包括具有多个存储单元的存储单元阵列和位线读出放大器，该位线读出放大器被配置为放大来自存储单元阵列的存储单元的一对位线上的数据，并将放大数据提供到 数据线和补充数据线。 有源负载电路包括电连接在数据线和电压源之间的第一负载装置，其中第一负载装置的电阻响应于数据线的电压电平而变化。 有源负载电路还包括电连接在互补数据线和电压源之间的第二负载装置，其中第二负载装置的电阻响应补充数据线的电压电平而变化。 还讨论了相关方法。

公开(公告)号：US06795372B2

公开(公告)日：2004-09-21

申请号：US10389482

申请日：2003-03-14

申请人： Myeong-o Kim ,  Chi-wook Kim ,  Sung-min Seo

发明人： Myeong-o Kim ,  Chi-wook Kim ,  Sung-min Seo

IPC分类号： G11C800

CPC分类号： G11C7/18 ,  G11C7/065 ,  G11C2207/065

摘要： Bit line sense amplifier driving control circuits and methods for synchronous DRAMs selectively supply and suspend supply of operating voltages for bit line sense amplifiers. More specifically, a synchronous DRAM includes a memory cell array including at least a first column block and a second column block that are divided according to column address, first bit line sense amplifiers that are configured to sense data that is output from the first column block of the memory cell array, and second bit line sense amplifiers that are configured to sense data that is output from the second column block of the memory cell array. A bit line sense amplifier driving control circuit or method is responsive to a row address select signal, to supply an operating voltage to the first and second bit line sense amplifiers, and is responsive to a column select signal that selects a column address in the first column block, to suspend supplying an operating voltage to the second bit line sense amplifiers.

摘要翻译： 用于同步DRAM的位线读出放大器驱动控制电路和方法选择性地供给和暂停供给位线读出放大器的工作电压。 更具体地，同步DRAM包括存储单元阵列，该存储单元阵列至少包括根据列地址划分的第一列块和第二列块，第一位线读出放大器被配置为感测从第一列块输出的数据 以及被配置为感测从存储单元阵列的第二列块输出的数据的第二位线读出放大器。 位线读出放大器驱动控制电路或方法响应于行地址选择信号，向第一和第二位线读出放大器提供工作电压，并响应列选择信号，该列选择信号选择第一位 列块，以暂停向第二位线读出放大器提供工作电压。

公开(公告)号：US06636998B1

公开(公告)日：2003-10-21

申请号：US09610498

申请日：2000-07-05

申请人： Jae Woong Lee ,  Myeong O Kim

发明人： Jae Woong Lee ,  Myeong O Kim

IPC分类号： G01R3128

CPC分类号： G11C29/12 ,  G11C29/40 ,  G11C2029/0405 ,  G11C2029/2602

摘要： A semiconductor memory device and a parallel bit test method thereof comprises a memory cell array having a plurality of memory cells, an address generator for accessing memory cells of the memory cell array in response to externally applied addresses; a test mode setting register for storing an externally applied test mode setting command; a test pattern data register for storing test pattern data applied from the test mode setting register and for outputting test pattern data at the time of performing a read command; and a comparator for comparing data read from the memory cells of the memory cell array with data of corresponding bits of test pattern data output from the test pattern data register and for generating test result data. Accordingly, the device is adapted for correctly detecting and distinguishing defective memory cells, and is amenable to performing bit tests using various non-uniform test pattern data.

摘要翻译： 半导体存储器件及其并行位测试方法包括具有多个存储器单元的存储单元阵列，响应于外部施加的地址而访问存储单元阵列的存储单元的地址生成器; 用于存储外部施加的测试模式设置命令的测试模式设置寄存器; 测试模式数据寄存器，用于存储从测试模式设置寄存器应用的测试模式数据，并用于在执行读取命令时输出测试模式数据; 以及比较器，用于将从存储单元阵列的存储单元读取的数据与从测试图案数据寄存器输出的测试图形数据的相应位的数据进行比较并产生测试结果数据。 因此，该装置适于正确地检测和区分有缺陷的存储单元，并且适于使用各种不均匀的测试图案数据进行比特测试。

公开(公告)号：US07570529B2

公开(公告)日：2009-08-04

申请号：US11830142

申请日：2007-07-30

申请人： Myeong-O Kim ,  Soo-Hwan Kim ,  Jong-Cheol Lee

发明人： Myeong-O Kim ,  Soo-Hwan Kim ,  Jong-Cheol Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/005

摘要： A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to sense and amplify a signal of the bit line, and a calibration circuit calibrating a voltage level of the bit line based on a logic threshold value of the bit line sense amplifier. The bit line sense amplifier senses and amplifies the signal of the bit line after the voltage level of the bit line is calibrated. The bit line sense amplifier may include a 2-stage cascade latch, which includes a first inverter having an input terminal connected with the bit line; and a second inverter which has an input terminal connected with an output terminal of the first inverter and an output terminal connected with the bit line and is enabled/disabled in response to a sensing control signal. The calibration circuit includes a switch element that is connected between the output terminal of the first inverter and the bit line and is turned on or off in response to a calibration control signal.

摘要翻译： 半导体存储器件的读出放大器电路及其操作方法，其中读出放大器电路包括与位线连接的位线读出放大器，以检测和放大位线的信号，校准电路校准 基于位线读出放大器的逻辑阈值的位线的电压电平。 位线检测放大器在校准位线的电压电平后，感测并放大位线的信号。 位线读出放大器可以包括2级级联锁存器，其包括具有与位线连接的输入端的第一反相器; 以及第二反相器，其具有与第一反相器的输出端子连接的输入端子和与位线连接的输出端子，并且响应于感测控制信号而被允许/禁止。 校准电路包括开关元件，其连接在第一反相器的输出端和位线之间，并响应于校准控制信号而导通或截止。

公开(公告)号：US20080159037A1

公开(公告)日：2008-07-03

申请号：US12004291

申请日：2007-12-20

申请人： Jong-Cheol Lee ,  Myeong-O Kim

发明人： Jong-Cheol Lee ,  Myeong-O Kim

IPC分类号： G11C7/08

CPC分类号： G11C7/08 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096

摘要： A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level is disclosed. The semiconductor memory device includes a sense amplification enable signal control portion which receives an initial sense amplification enable signal, sequentially delays the initial sense amplification enable signal by a plurality of predetermined time periods and selectively outputs a plurality of delayed sense amplification enable signals in view of both an operation speed and a manufacturing yield of a semiconductor memory device; a plurality of clocked sense amplifiers which each receive an output signal of the I/O sense amplifier, amplify the output signal of the I/O sense amplifier in response to each of the plurality of delayed sense amplification enable signals, and sequentially output an output signal of a power voltage level or a ground voltage level in response; and a previous-step output driving circuit which sequentially receives the output signals of the plurality of clocked sense amplifiers, delays the output signals of the plurality of clocked sense amplifiers by a predetermined time period, and then intercepts an output of the clocked sense amplifier of a previous step.

摘要翻译： 一种半导体存储器件，包括位线读出放大器，用于放大与存储在存储单元的电容器中的电荷相对应的电压并输出放大电压;以及I / O读出放大器，用于接收位线读出放大器的输出，放大 公开了输出的电压电平并输出放大的电压电平。 半导体存储器件包括读出放大使能信号控制部分，其接收初始读出放大使能信号，将初始读出放大使能信号顺序地延迟多个预定时间周期，并且选择性地输出多个延迟读出放大使能信号， 半导体存储器件的操作速度和制造成品率; 多个时钟读出放大器，其各自接收I / O读出放大器的输出信号，响应于多个延迟读出放大使能信号中的每一个放大I / O读出放大器的输出信号，并依次输出输出 电源电压信号或接地电压电平响应; 以及前级输出驱动电路，其依次接收多个时钟读出放大器的输出信号，将多个时钟读出放大器的输出信号延迟预定的时间周期，然后截取时钟感测放大器的输出 前一步。

公开(公告)号：US20080151664A1

公开(公告)日：2008-06-26

申请号：US11830142

申请日：2007-07-30

申请人： Myeong-O Kim ,  Soo-Hwan Kim ,  Jong-Cheol Lee

发明人： Myeong-O Kim ,  Soo-Hwan Kim ,  Jong-Cheol Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/005

摘要： A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to sense and amplify a signal of the bit line, and a calibration circuit calibrating a voltage level of the bit line based on a logic threshold value of the bit line sense amplifier. The bit line sense amplifier senses and amplifies the signal of the bit line after the voltage level of the bit line is calibrated. The bit line sense amplifier may include a 2-stage cascade latch, which includes a first inverter having an input terminal connected with the bit line; and a second inverter which has an input terminal connected with an output terminal of the first inverter and an output terminal connected with the bit line and is enabled/disabled in response to a sensing control signal. The calibration circuit includes a switch element that is connected between the output terminal of the first inverter and the bit line and is turned on or off in response to a calibration control signal.

摘要翻译： 半导体存储器件的读出放大器电路及其操作方法，其中读出放大器电路包括与位线连接的位线读出放大器，以检测和放大位线的信号，校准电路校准 基于位线读出放大器的逻辑阈值的位线的电压电平。 位线检测放大器在校准位线的电压电平后，感测并放大位线的信号。 位线读出放大器可以包括2级级联锁存器，其包括具有与位线连接的输入端的第一反相器; 以及第二反相器，其具有与第一反相器的输出端子连接的输入端子和与位线连接的输出端子，并且响应于感测控制信号而被允许/禁止。 校准电路包括开关元件，其连接在第一反相器的输出端和位线之间，并响应于校准控制信号而导通或截止。

公开(公告)号：US07263026B2

公开(公告)日：2007-08-28

申请号：US11327247

申请日：2006-01-05

申请人： Min-Soo Kim ,  Myeong-O Kim ,  Jae-Woong Lee

发明人： Min-Soo Kim ,  Myeong-O Kim ,  Jae-Woong Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A control unit for a semiconductor memory device, a semiconductor memory device and a method for controlling the same. The control unit of a semiconductor memory device includes control signal circuits, each control signal circuit to receive a master signal and to generate at least one of a plurality of control signals in response to the master signal, each of the plurality of core control signals to be generated after a delay specific to the core control signals after a transition of the master signal, the plurality of control signals to control the semiconductor memory device.

摘要翻译： 一种用于半导体存储器件的控制单元，半导体存储器件及其控制方法。 半导体存储器件的控制单元包括控制信号电路，每个控制信号电路接收主信号并响应于主信号产生多个控制信号中的至少一个，多个核心控制信号中的每一个至 在主信号转换之后的核心控制信号的特定延迟之后产生多个控制信号以控制半导体存储器件。