公开(公告)号：US07310498B2

公开(公告)日：2007-12-18

申请号：US10410088

申请日：2003-04-09

Applicant: Trenton B. Henry ,  Klaas Wortel ,  Guy A. Stewart ,  Henry Wurzburg ,  James R. MacDonald

Inventor： Trenton B. Henry ,  Klaas Wortel ,  Guy A. Stewart ,  Henry Wurzburg ,  James R. MacDonald

IPC: H04B7/00

CPC classification number: H04W36/06 ,  H04W8/005 ,  H04W48/08

Abstract: A system and method for maintaining communications with a radio frequency (RF) peripheral device such as an RF input device and an RF output device. A computer may search for an RF peripheral device by transmitting a signal request on available channels until a response is received from an RF peripheral device. If the RF channel becomes busy and/or jammed, the RF peripheral device may tune into a predetermined channel while the computer scans for another channel to use. Once the computer finds a better channel, the computer may go to the predetermined channel and broadcast the new channel location to the RF peripheral device. In addition, if an RF signal arrives incomplete or corrupt, the computer may transmit a negative acknowledgement to the RF peripheral device, which may retransmit the previous RF signal.

Abstract translation: 用于维持与诸如RF输入设备和RF输出设备的射频（RF）外围设备的通信的系统和方法。 计算机可以通过在可用信道上发送信号请求来搜索RF外围设备，直到从RF外围设备接收到响应。 如果RF信道变得忙和/或卡住，则RF外围设备可以调谐到预定信道中，同时计算机扫描另一个信道使用。 一旦计算机找到更好的信道，则计算机可以进入预定信道并将新的信道位置广播到RF外围设备。 此外，如果RF信号到达不完整或损坏，则计算机可以向RF外围设备发送否定确认，RF外设可以重传先前的RF信号。

公开(公告)号：US07222252B2

公开(公告)日：2007-05-22

申请号：US10366189

申请日：2003-02-13

Applicant: Drew J. Dutton ,  James R. MacDonald ,  Stephen Cox

Inventor： Drew J. Dutton ,  James R. MacDonald ,  Stephen Cox

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3215

Abstract: A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the user probably has both hands on a keyboard, the computer system may generate a signal to the computer mouse to enter a low power state. The computer system may use prior usage for a user to determine when current usage indicates that the second peripheral device is not being used. After the second peripheral device is placed in a low power state, the computer system may generate a signal to the second peripheral device to return to a normal power state when the computer system determines that the user no longer has both hands occupied.

Abstract translation: 一种用于监视外围设备的使用并且当使用指示没有使用第二外围设备时将第二外围设备置于低功率状态的系统和方法。 例如，如果计算机系统检测到用户的当前打字率指示用户可能在键盘上具有双手，则计算机系统可以向计算机鼠标生成信号以进入低功率状态。 计算机系统可以使用用户的先前使用来确定当前使用情况何时指示第二外围设备未被使用。 在第二外围设备处于低功率状态之后，当计算机系统确定用户不再具有双手时，计算机系统可以向第二外围设备产生信号以返回到正常的功率状态。

公开(公告)号：US5933620A

公开(公告)日：1999-08-03

申请号：US623022

申请日：1996-03-28

Applicant: Sherman Lee ,  James R. MacDonald ,  Michael T. Wisor

Inventor： Sherman Lee ,  James R. MacDonald ,  Michael T. Wisor

IPC: G06F1/00 ,  G06F11/00 ,  G06F21/00 ,  G06F12/14

CPC classification number: G06F21/73 ,  G06F11/006 ,  G06F21/575 ,  G06F2207/7219 ,  G06F2211/007

Abstract: A method and apparatus for providing a microprocessor serial number. A small, nonvolatile random access memory is packaged with the CPU die to provide a storage space for a CPU serial number which can be programmed before leaving the factory. Both the CPU die and the nonvolatile RAM die reside within the cavity of the package. Connection between the two die is provided by conventional wire bonding.

Abstract translation: 一种用于提供微处理器序列号的方法和装置。 一个小型的，非易失性的随机存取存储器与CPU管芯一起封装，为出厂前可编程的CPU序列号提供存储空间。 CPU管芯和非易失性RAM管芯都位于封装的腔内。 两个管芯之间的连接由常规引线接合提供。

公开(公告)号：US5913224A

公开(公告)日：1999-06-15

申请号：US805554

申请日：1997-02-26

Applicant: James R. MacDonald

Inventor： James R. MacDonald

IPC: G06F12/12 ,  G06F12/14

CPC classification number: G06F12/126

Abstract: A computer system is disclosed which provides for execution of real-time code from cache memory. A cache management unit provides the real-time code to the cache memory from system memory upon a initiation of a read operation by a processor. Once in cache memory, the processor executes the real-time code from cache memory instead of system memory. The cache management unit detects read hits to cache each time the processor requests an instruction of code that is stored in the cache memory. Lock bits associated with each line of cache lock the contents of the line preventing the line from being overwritten under normal cache operation in which the least most recently used cached data is replaced by presently accessed data. Alternatively, one of a plurality of cache data ways may be dedicated to storing real-time code. Real-time code stored in the dedicated data way is not replaceable and thus is locked.

Abstract translation: 公开了一种提供从高速缓存存储器执行实时代码的计算机系统。 高速缓存管理单元在处理器开始读取操作时，从系统存储器向高速缓冲存储器提供实时代码。 一旦处于高速缓冲存储器中，处理器就从高速缓冲存储器而不是系统存储器执行实时代码。 每当处理器请求存储在高速缓冲存储器中的代码指令时，高速缓存管理单元检测读取命中以缓存。 与每行高速缓存相关联的锁定位锁定线路的内容，防止在正常高速缓存操作中覆盖该行，其中最近最少使用的缓存数据被当前访问的数据替换。 或者，多个高速缓存数据路径中的一个可专用于存储实时代码。 以专用数据方式存储的实时代码不可更换，因此被锁定。

公开(公告)号：US5696927A

公开(公告)日：1997-12-09

申请号：US576100

申请日：1995-12-21

Applicant: James R. MacDonald ,  Drew Dutton ,  Steve Cox

Inventor： James R. MacDonald ,  Drew Dutton ,  Steve Cox

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/023 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/401

Abstract: A memory paging and compression system for a computer having a memory and an execution unit includes an address mapping hierarchy, a compressed page mapping hierarchy, a translation lookaside buffer, and a compression/decompression component. The address mapping hierarchy includes page tables having page table entries which map from a first portion of virtual addresses to respective pages in physical memory. The compressed page mapping hierarchy includes compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory. The translation lookaside buffer caches recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory. The compression/decompression component includes a compression/decompression engine coupled between a memory and an execution unit for alternately compressing and decompression pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer. The address mapping hierarchy and compressed page mapping hierarchy may be represented in memory and the compression/decompression component may further include a decompression fault handler and a compression fault handler, each executable on the execution unit.

Abstract translation: 用于具有存储器和执行单元的计算机的存储器寻呼和压缩系统包括地址映射层级，压缩页面映射层级，翻译后端缓冲器和压缩/解压缩组件。 地址映射层次结构包括具有从虚拟地址的第一部分映射到物理存储器中的相应页面的页表条目的页表。 压缩页面映射层级包括具有从虚拟地址的第一部分映射到物理存储器中的相应压缩页面的压缩页表项的压缩页表。 翻译后备缓冲区最近缓存了从虚拟地址的第一部分到物理存储器中各页的映射关系。 压缩/解压缩部件包括耦合在存储器和执行单元之间的压缩/解压缩引擎，用于与存储器中的交替压缩和解压缩页面分别对应于来自翻译后备缓冲器的溢出和负载。 地址映射层级和压缩页映射层次可以在存储器中表示，并且压缩/解压缩组件还可以包括解压缩故障处理程序和压缩故障处理程序，每个执行单元都可执行。

公开(公告)号：US5600839A

公开(公告)日：1997-02-04

申请号：US131092

申请日：1993-10-01

Applicant: James R. MacDonald

Inventor： James R. MacDonald

IPC: G06F13/42 ,  G06F1/04 ,  G06F1/32

CPC classification number: G06F1/3215 ,  G06F1/324 ,  Y02B60/1217

Abstract: A system and method for controlling a peripheral bus clock signal through a slave device are provided that accommodate a power conservation scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other central resource. Prior to stopping the peripheral bus clock signal, an indicator signal is generated at a clock request line by a clock control circuit. If the slave device continues to require the peripheral bus clock signal, the slave device responsively generates a clock request signal. The clock control circuit receives the clock request signal and accordingly prevents the peripheral bus clock signal from stopping. The system may further allow an alternate bus master to assert the clock request signal to re-start the peripheral bus clock signal after it has stopped. The alternate bus master can thereby generate a synchronous bus request signal to attain mastership of the peripheral bus. As a result of the system, a slave device can prevent the stopping of the peripheral bus clock signal at the completion of a peripheral bus cycle if the clock signal continues to be required. The system further accommodates a power management scheme in which the peripheral bus clock signal can be stopped and that allows an alternate bus master to re-start the peripheral bus clock signal.

Abstract translation: 提供了一种用于通过从设备控制外围总线时钟信号的系统和方法，其适应例如由电源管理单元或其他中央资源停止外部总线时钟信号的功率节省方案。 在停止外设总线时钟信号之前，时钟控制电路在时钟请求线产生指示信号。 如果从设备继续需要外设总线时钟信号，则从设备响应地产生时钟请求信号。 时钟控制电路接收时钟请求信号，从而防止外设总线时钟信号停止。 该系统还可以允许备用总线主机断言时钟请求信号，以在其外围总线时钟信号停止之后重新启动外围总线时钟信号。 因此，备用总线主机可以产生同步总线请求信号，以实现外设总线的掌握。 作为该系统的结果，如果继续需要时钟信号，则从设备可以防止外围总线周期完成时外围总线时钟信号的停止。 该系统进一步适应电源管理方案，其中可以停止外设总线时钟信号，并允许备用总线主机重新启动外设总线时钟信号。

公开(公告)号：US5249287A

公开(公告)日：1993-09-28

申请号：US577918

申请日：1990-08-31

Applicant: James R. MacDonald ,  Doug Gephardt

Inventor： James R. MacDonald ,  Doug Gephardt

IPC: G06F3/023

CPC classification number: G06F3/023

Abstract: A keyboard interface is implemented in an integrated circuit and supports first and second types of keyboards and associated interfaces from a single set of integrated circuit terminals. The keyboard interface includes a first keyboard logic responsive to a first mode select signal for providing a first set of control signals for supporting the first type of keyboard and second keyboard logic responsive to a second mode select signal for providing a second set of control signals for supporting the second type of keyboard. A multiplexer couples the first set of control signals to the set of terminals responsive to the first mode select signal and couples the second set of control signals to the set of terminals responsive to the second mode select signal. A keyboard register provides the first or second mode select signals to the first and second keyboard logic and the multiplexer.

Abstract translation: 键盘接口在集成电路中实现并且支持来自单组集成电路终端的第一和第二类型的键盘和相关联的接口。 键盘接口包括响应于第一模式选择信号的第一键盘逻辑，用于提供用于支持第一类型的键盘的第一组控制信号和响应于第二模式选择信号的第二键盘逻辑，以提供第二组控制信号 支持第二种键盘。 多路复用器响应于第一模式选择信号将第一组控制信号耦合到终端集合，并响应于第二模式选择信号将第二组控制信号耦合到终端集合。 键盘寄存器提供第一或第二模式选择信号给第一和第二键盘逻辑和复用器。

公开(公告)号：US5241665A

公开(公告)日：1993-08-31

申请号：US996500

申请日：1992-12-23

Applicant: James R. MacDonald

Inventor： James R. MacDonald

IPC: G06F12/06

CPC classification number: G06F12/0653 ,  G06F12/0607

Abstract: A memory bank comparator system in a memory system including a plurality of memory banks determines, on a cycle-by-cycle basis, whether a memory address is valid, which one of the memory banks is being addressed, the type of memory bank being addressed, and whether memory bank interleaving is possible. The memory bank comparator system includes a factor assignor which provides a factor for each of the memory banks corresponding to the maximum number of storage locations within each bank, an adder for adding the factors together to provide a sum for each memory bank corresponding to the maximum number of storage locations within its respective memory bank plus the sum of the maximum number of storage locations of the memory banks which precede it, and an address comparator for comparing the memory address to each sum for providing an output indicating which one of the memory banks is being addressed.

Abstract translation: 包括多个存储器组的存储器系统中的存储器组比较器系统在逐周期的基础上确定存储器地址是否有效，正在寻址存储器组中的哪一个，存储器组的类型被寻址 ，以及是否可以存储器组交错。 存储器组比较器系统包括因子分配器，该因子分配器为每个存储体中的每个存储体提供与每个存储单元中的最大存储位置数量相对应的因子;加法器，用于将这些因子相加在一起，以提供与最大值相对应的每个存储体的和 其各自存储体中的存储位置的数量加上其前面的存储体的最大存储位置数之和;以及地址比较器，用于将存储器地址与每个和比较，以提供指示哪个存储体 正在处理中。

公开(公告)号：US5218681A

公开(公告)日：1993-06-08

申请号：US576061

申请日：1990-08-31

Applicant: Douglas D. Gephardt ,  James R. MacDonald

Inventor： Douglas D. Gephardt ,  James R. MacDonald

IPC: G06F13/36 ,  G06F13/14 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/14

Abstract: An apparatus for use with a host computing system for controlling access to a first data bus which is external of the host computing system and which first data bus is operatively connected with a second data bus internal of the host computing system. The apparatus comprises a local processing unit which is configured substantially the same as the host processing unit and is driven by a separate local program distinct from the host processing program driving the host processing unit. The apparatus further comprises a supplemental processing circuit for processing information, which supplemental processing circuit is responsive to the host processing unit and to the local processing unit to determine whether the host processing unit or the local processing unit has operative access to the first data bus. In its preferred embodiment, the first data bus and the second data bus are operatively connected by a configurable buffer circuit for effecting data bus connection. Further, in the preferred embodiment of the present invention, the supplemental processing circuit generates an intervention signal in response to the local processing unit, the buffer circuit responding to the intervention signal by configuring appropriately to provide operative access by the apparatus of the second data bus.

公开(公告)号：US08572420B2

公开(公告)日：2013-10-29

申请号：US11071961

申请日：2005-03-04

Applicant: Drew J. Dutton ,  James R. MacDonald ,  Henry Wurzburg

Inventor： Drew J. Dutton ,  James R. MacDonald ,  Henry Wurzburg

IPC: G06F3/00

CPC classification number: G06K19/07732 ,  G06K7/0013 ,  G06K7/0086 ,  G06K19/0701

Abstract: In various embodiments, a computer system may include a computer controller to send and/or receive sideband signals to/from a USB device. In some embodiments, the USB device may include a USB controller to send/receive sideband signals to/from the computer controller. The computer controller and USB controller may allow communications between the computer system and the USB device when either of the computer system or USB device is in a low power state. The sideband signal sent between the computer system and the USB device may trigger the other of the computer system or USB device to enter a normal power state. In some embodiments, the computer controller and/or USB controller may be further coupled to a memory to buffer data to be sent to the computer system or USB device after the computer system or USB device returns to a normal power state.

Abstract translation: 在各种实施例中，计算机系统可以包括计算机控制器来向/从USB设备发送和/或接收边带信号。 在一些实施例中，USB设备可以包括用于向计算机控制器发送/接收边带信号的USB控制器。 当计算机系统或USB设备中的任一个处于低功率状态时，计算机控制器和USB控制器可以允许计算机系统和USB设备之间的通信。 在计算机系统和USB设备之间发送的边带信号可能触发计算机系统或USB设备中的另一个进入正常的电源状态。 在一些实施例中，计算机控制器和/或USB控制器可以进一步耦合到存储器，以在计算机系统或USB设备恢复到正常功率状态之后缓冲要发送到计算机系统或USB设备的数据。