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公开(公告)号：US20250150246A1
公开(公告)日：2025-05-08
申请号：US19002187
申请日：2024-12-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chanho AN , Jonghyung KWUN , Jinhyuk LEE , Jonghyune KIM , Taekhoon KIM , Jinwoo YANG , Hyoungju JI , Seunghoon CHOI , Youngkyu CHOI
IPC: H04L5/14 , H04W8/24 , H04W72/0457 , H04W72/21
Abstract: The disclosure relates to a 5G or 6G communication system for supporting higher data transmission rates. A method performed by a base station configured to support a time division duplex (TDD) system in a wireless communication system, according to various embodiments of the present disclosure, may comprise: transmitting, to a terminal, resource configuration information including a first cross division duplex-uplink (XDD-UL) section; determining whether a change of the first XDD-UL section is necessary; identifying a second XDD-UL section based on the determination result; transmitting, to the terminal, information about the second XDD-UL section; and receiving, from the terminal, an uplink signal on the basis of the first XDD-UL section and/or the second XDD-UL section.
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公开(公告)号：US20250149942A1
公开(公告)日：2025-05-08
申请号：US18813718
申请日：2024-08-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Woong HWANG
Abstract: A motor may include a shaft, a stator and a rotor. The rotor may include a plurality of magnets, a casing and a rotor core. The rotor core may include a plurality of first core layers and a plurality of second core layers. The first core layer may include a base part through which the shaft passes, a plurality of core parts spaced apart from each other along a circumferential direction of the base part, and a plurality of bridge parts configured so that each of the plurality of bridge parts extends from a corresponding core part of the plurality of core parts toward the base part, and is bent toward the corresponding core part.
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公开(公告)号：US20250149773A1
公开(公告)日：2025-05-08
申请号：US19013690
申请日：2025-01-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungjoon KIM , Heejin PARK , Kyunghoon MOON , Sungsoo KIM , Yongyoun KIM , Youngjoon LIM
Abstract: An electronic device is provided. The electronic device includes a first housing forming at least a part of a side surface of the electronic device, wherein a first opening is formed in the first housing, a first conductive structure formed on the inside the first opening, and an antenna module, wherein the antenna module includes a printed circuit board (PCB), a plurality of conductive patches disposed on the PCB to face the first opening, and a wireless communication circuit, wherein, as the wireless communication circuit is configured to feed power to the plurality of conductive patches, a first electric path is formed in the first conductive structure which is spaced apart from the plurality of conductive patches, and wherein a radio frequency (RF) signal generated based on the first electric path is radiated to an outside of the electronic device.
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公开(公告)号：US20250149520A1
公开(公告)日：2025-05-08
申请号：US18780675
申请日：2024-07-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junghoon Kang , Daegon Kim
IPC: H01L25/18 , G02B6/12 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/538 , H01L27/144
Abstract: A semiconductor package including a package substrate, a plurality of chiplets located on the package substrate, the plurality of chiplets including a photonics chip and a semiconductor chip located on the photonics chip, and a plurality of photonics bridge chips located on the package substrate. The plurality of chiplets are spaced apart from each other in a horizontal direction, and each of the plurality of photonics bridge chips is located between the plurality of chiplets.
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公开(公告)号：US20250149516A1
公开(公告)日：2025-05-08
申请号：US18780730
申请日：2024-07-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junghoon Kang , Daegon Kim
IPC: H01L25/10 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/49 , H01L23/498 , H01L23/538 , H01L27/144 , H10B80/00
Abstract: A semiconductor package including a package substrate, a plurality of photonics bridge chips located on the package substrate, a molding layer located on the package substrate, surrounding the plurality of photonics bridge chips, and including a plurality of via electrodes, and a plurality of chiplets located on the molding layer and the plurality of photonics bridge chips, the chiplets each including a photonics chip and a semiconductor chip located on the photonics chip, wherein the plurality of chiplets are spaced apart from each other in a horizontal direction, and at least two chiplets adjacent to each other from among the plurality of chiplets overlap one photonics bridge chip from among the plurality of photonics bridge chips in a vertical direction.
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Patent Agency Ranking
公开(公告)号：US20250149494A1
公开(公告)日：2025-05-08
申请号：US18940264
申请日：2024-11-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaekyung Yoo , Jinwoo Park , Kyonghwan Koh , Woohyeong Kim , Taeryong Kim
IPC: H01L23/00 , H01L21/56 , H01L23/29 , H01L23/48 , H01L23/498 , H01L25/065 , H01L25/10 , H01L25/18 , H10B80/00
Abstract: A semiconductor package includes a first substrate, a first semiconductor chip on an upper surface of the first substrate, a first bump between the first substrate and the first semiconductor chip, a first underfill layer that fills a center portion of a space between the first substrate and the first semiconductor chip, and a first molding member that covers an upper surface and side surfaces of the first semiconductor chip, and fills a periphery portion of the space between the first substrate and the first semiconductor chip, wherein a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first underfill layer in the space between the first substrate and the first semiconductor chip.
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公开(公告)号：US20250149443A1
公开(公告)日：2025-05-08
申请号：US18533031
申请日：2023-12-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SUJIN PARK , HONGSOO KIM , HEE-SUNG KAM , BYUNGJOO GO , Janghee JUNG
IPC: H01L23/528 , H01L23/522 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/41 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40 , H10B80/00
Abstract: A semiconductor device may include a source structure including a cell region and an extension region adjacent to the cell region, a gate stack in the cell and extension regions, a penetration contact disposed in the extension region, a stepwise insulating layer disposed on the gate, and an interconnection structure on the stepwise insulating layer. The interconnection structure may include a first interconnection insulating layer, a first lower conductive pattern in the first interconnection insulating layer, a capping layer on the first interconnection insulating layer, and a via structure penetrating the capping layer. The via structure may include a plurality of first vias connected to the first lower conductive pattern and connected to an upper conductive pattern, and the first vias may be disposed in the extension region.
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公开(公告)号：US20250149340A1
公开(公告)日：2025-05-08
申请号：US18678183
申请日：2024-05-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungchan Yun , Kang-Ill Seo
IPC: H01L21/28 , H01L21/822 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775
Abstract: Transistor devices are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor that is on top of the lower transistor. Moreover, the transistor device includes a gate-cut on the substrate, adjacent the transistor stack. The gate-cut has a first sloped sidewall and a second sloped sidewall that is opposite the first sloped sidewall. Related methods of forming transistor devices are also provided.
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公开(公告)号：US20250149311A1
公开(公告)日：2025-05-08
申请号：US18762910
申请日：2024-07-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junho IM , Younseon WANG , Keonwoo KIM , Youngjin NOH , Dougyong SUNG , Wonhee LEE , Sungwook JUNG
IPC: H01J37/32 , C23C16/458 , H01L21/683
Abstract: A substrate processing apparatus may include a chucking member configured to support a substrate, a base plate configured to support the chucking member, a bonding layer located between the chucking member and the base plate, the bonding layer configured to adhere the chucking member to the base plate, a coating layer on an outer side surface of the bonding layer, and a bonding protective member surrounding an outer side surface of the coating layer, wherein the coating layer conformally covers the outer side surface of the bonding layer.
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公开(公告)号：US20250149301A1
公开(公告)日：2025-05-08
申请号：US19009570
申请日：2025-01-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chan Hoon PARK , Jung Hwan UM , Jin Young PARK , Ho Yong PARK , Jin Young BANG , Jong Woo SUN , Sang Jean JEON , Je Woo HAN
Abstract: A plasma processing apparatus may include a support configured to receive a substrate, a gas distribution plate (GDP) including a plurality of nozzles facing the support, a main splitter configured to supply a process gas, and an additional splitter configured to supply an acceleration gas or a deceleration gas. The plurality of nozzles may include a plurality of central nozzles, a plurality of outer nozzles, a plurality of middle nozzles configured to spray the process gas and the acceleration gas, a plurality of first nozzles, and a plurality of second nozzles.
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