公开(公告)号：US10936214B2

公开(公告)日：2021-03-02

申请号：US16441338

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Prasoonkumar Surti ,  Aravindh V. Anantaraman ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu

IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/3225 ,  G11C11/406 ,  G11C11/4074

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a memory comprising one or more physical memory chips, and a processor to implement a working set monitor to monitor a working set resident in the one or more physical memory chips. The working set monitor is to adjust a number of the physical memory chips that are powered on based on a size of the working set.

公开(公告)号：US10929950B2

公开(公告)日：2021-02-23

申请号：US16599250

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Hiroshi Akiba

IPC: G06T1/60 ,  G06T9/00

Abstract: Embodiments provide for a graphics processing apparatus including a cache memory and logic coupled to the cache memory to compress color data output from the first cache memory. In one embodiment the cache memory is a render cache. In one embodiment the cache memory is a victim data cache. In one embodiment the first cache memory is a render cache coupled to a victim data cache and logic is configured to compress color data evicted from the render cache and the victim data cache. The compression can include a target compression ratio to which the data is to be compressed.

公开(公告)号：US10929749B2

公开(公告)日：2021-02-23

申请号：US15494948

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Narayan Srinivasa ,  Joydeep Ray ,  Nicolas C. Galoppo Von Borries ,  Ben Ashbaugh ,  Prasoonkumar Surti ,  Feng Chen ,  Barath Lakshmanan ,  Elmoustapha Ould-Ahmed-Vall ,  Liwei Ma ,  Linda L. Hurd ,  Abhishek R. Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Dukhwan Kim ,  Altug Koker ,  Nadathur Rajagopalan Satish

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/28 ,  G06F9/302 ,  G06F15/00 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

公开(公告)号：US20210042983A1

公开(公告)日：2021-02-11

申请号：US17069406

申请日：2020-10-13

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Joydeep Ray ,  Michael J. Norris

IPC: G06T15/00 ,  G06T11/40

Abstract: One embodiment provides for a data processing system comprising a memory module to store a multisample render target, the multisample render target to store multiple sample locations for each pixel in a set of pixels and a general-purpose graphics processor including a hardware graphics rendering pipeline to generate pixel color data to be output to the multisample render target, a multisample antialiasing compressor to request allocation of one or more planes to store color data for a set of sample locations of a pixel in the set of pixels, and a memory allocator to allocate memory to store color data associated with the multisample render target. The memory allocator can merge a memory allocation for multiple pixels having a sample associated with a same color value.

公开(公告)号：US20210035259A1

公开(公告)日：2021-02-04

申请号：US16930935

申请日：2020-07-16

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Saikat Mandal ,  Karol A. Szerszen ,  Saurabh Sharma ,  Vamsee Vardhan Chivukula ,  Abhishek R. Appu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Altug Koker

IPC: G06T1/60 ,  G06F12/0875 ,  G06T1/20

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.

公开(公告)号：US10909037B2

公开(公告)日：2021-02-02

申请号：US15493404

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Altug Koker ,  James A. Valerio ,  Prasoonkumar Surti

IPC: G09G5/36 ,  G06F12/0844 ,  G06T1/60

Abstract: A mechanism is described for facilitating memory address compression at computing devices. A method of embodiments, as described herein, includes coalescing slot addresses across multiple messages received from an execution unit, where the slot addresses are coalesced in groups based on memory cacheline addresses such that each of a set of slot addresses in a group have a memory cacheline address in common between them. The method may further include outputting the memory cacheline addresses.

公开(公告)号：US10908905B2

公开(公告)日：2021-02-02

申请号：US16599239

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Abhishek R. Appu ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu

IPC: G06F9/30 ,  G09G5/393 ,  G06T1/60 ,  G06T1/20 ,  G06F9/50 ,  G09G5/36 ,  G06F12/0842

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first number of threads to be scheduled for each context of a plurality of contexts in a multi-context processing system, allocate a second number of streaming multiprocessors (SMs) to the respective plurality of contexts, and dispatch threads from the plurality of contexts only to the streaming multiprocessor(s) allocated to the respective plurality of contexts. Other embodiments are also disclosed and claimed.

公开(公告)号：US10902546B2

公开(公告)日：2021-01-26

申请号：US15493324

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Kiran C. Veernapu ,  Abhishek R. Appu ,  Prasoonkumar Surti ,  Arijit Mukhopadhyay ,  Altug Koker ,  Joydeep Ray

IPC: G06T1/20 ,  H04N9/804 ,  H04N9/808

Abstract: A mechanism is described for facilitating selective skipping of compression cycles in computing devices. A method of embodiments, as described herein, includes facilitating determining a first current output relating to compression of a current set of data to be same as a previous output from compression of a previous set of data, and turning off a compression engine to skip compression of the current set of data.

公开(公告)号：US10901647B2

公开(公告)日：2021-01-26

申请号：US16358463

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Nilay Mistry

IPC: G06F3/06 ,  G06F12/06

Abstract: An apparatus to facilitate copying surface data is disclosed. The apparatus includes copy engine hardware to receive a command to access surface data from a source location in memory to a destination location in the memory, divide the surface data into a plurality of surface data sub-blocks, process the surface data sub-blocks to calculate virtual addresses to which accesses to the memory are to be performed and perform the memory accesses.

公开(公告)号：US10817042B2

公开(公告)日：2020-10-27

申请号：US16144538

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Kinchit Desai ,  Sanjeev Jahagirdar ,  Prasoonkumar Surti ,  Joydeep Ray

IPC: G06F1/3237 ,  G06N3/04 ,  G06N3/08 ,  G06F1/3234 ,  G06F1/3206

Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.