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公开(公告)号：US11568790B2
公开(公告)日：2023-01-31
申请号：US16648515
申请日：2019-01-02
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G5/00 , G09G3/20 , G09G3/36 , G09G3/3266 , G11C19/28
Abstract: A shift register is provided, which may include a compensation selection circuit, a holding circuit, and N shift register circuits. The hold circuit may hold a blanking input signal. Each of the shift register circuits may include a blanking input circuit and an output circuit. The blanking input circuit may provide a blanking pull-down signal to a first node according to the blanking input signal and a blanking control signal. The output circuit may output a shift signal via a shift signal output terminal and output a first drive signal via a first drive signal output terminal according to a voltage of the first node. The compensation selection circuit may provide, according to a compensation selection control signal and the shift signal from one of the N shift register circuits, the blanking input signal to the holding circuit and the N shift register circuits.
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162.发明申请公开(公告)号：US20220383792A1
公开(公告)日：2022-12-01
申请号：US17819215
申请日：2022-08-11
Inventor： Xuehuan Feng , Yongqian Li
Abstract: The present application discloses a shift-register unit circuit including a first input sub-circuit configured to receive a display-input signal from a display-input terminal and input a display output-control signal to a first node based on the display-input signal during a display period of one cycle of displaying one frame of image. The shift-register unit circuit also includes a second input sub-circuit configured to receive a blank-input signal for charging a blank-control node, and configured to input a blank-output-control signal to the first node based on the blank-input signal during a blank period of the one cycle. The shift-register unit circuit further includes an output sub-circuit configured to output a hybrid signal controlled by the first node. The second input sub-circuit is also configured, before an end of the blank period, to receive a first blank-reset signal to reset the blank-control node.
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公开(公告)号：US11508295B2
公开(公告)日：2022-11-22
申请号：US17309360
申请日：2020-08-12
Inventor： Zhongyuan Wu , Yongqian Li , Can Yuan , Xuehuan Feng , Zhidong Yuan
IPC: G09G3/3225 , G11C19/28
Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, and a GOA circuit, a source electrode IC and PLG wires arranged on the base substrate, and the PLG wires connect the GOA circuit with the source electrode IC. The GOA circuit transmits a GOA signal, and the GOA signal comprises a cascade signal and a non-cascade signal. The PLG wires comprise a first PLG wire group and at least one second PLG wire group, the first PLG wire group transmits the cascade signal, the second PLG wire group transmits the non-cascade signal, a line width of the first PLG wire group is smaller than that of the second PLG wire group, and the first PLG wire group is located at a side of the second PLG wire group distal to an active area of the base substrate.
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公开(公告)号：US11482688B2
公开(公告)日：2022-10-25
申请号：US16762985
申请日：2019-07-05
Inventor： Can Yuan , Yongqian Li , Zhidong Yuan
Abstract: A display substrate including a plurality of light emitting elements respectively in a plurality of subpixels configured to emit light for image display is provided. A respective one of the plurality of subpixels includes a base substrate; a first auxiliary cathode; a passivation layer; a first insulating layer; a second auxiliary cathode; a second insulating layer; and a pixel definition layer. The display substrate has a cathode aperture extending through the pixel definition layer and an auxiliary cathode aperture extending through the first insulating layer and the passivation layer. A cathode of a respective one of the plurality of light emitting elements extends into the cathode aperture to electrically connect with the second auxiliary cathode. The second auxiliary cathode extends into the auxiliary cathode aperture to electrically connect with the first auxiliary cathode.
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165.发明授权公开(公告)号：US11468810B2
公开(公告)日：2022-10-11
申请号：US16612947
申请日：2019-06-28
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3266 , G09G3/20 , G11C19/28
Abstract: A shift-register unit circuit (100) includes a first input sub-circuit (120) configured to receive a display-input signal from a display-input terminal (STU2, VDD, VGH) and input a display output-control signal to a first node (Q) based on the display-input signal during a display period of one cycle of displaying one frame of image. The shift-register unit circuit (100) also includes a second input sub-circuit (110) configured to receive a blank-input signal for charging a blank-control node (H), and configured to input a blank-output-control signal to the first node (Q) based on the blank-input signal during a blank period of the one cycle. The shift-register unit circuit (100) further includes an output sub-circuit (130) configured to output a hybrid signal controlled by the first node (Q). The second input sub-circuit (110) is also configured, before an end of the blank period, to receive a first blank-reset signal to reset the blank-control node (H).
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Patent Agency Ranking
公开(公告)号：US20220319393A1
公开(公告)日：2022-10-06
申请号：US17844899
申请日：2022-06-21
Inventor： Xuehuan Feng , Yongqian Li
Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.
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公开(公告)号：US11450267B2
公开(公告)日：2022-09-20
申请号：US16621937
申请日：2019-03-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Dongxu Han , Tieshi Wang , Zhongyuan Wu , Yongqian Li , Pan Xu , Jinxia Hu
IPC: G09G3/3225
Abstract: Brightness compensation method and apparatus for pixel point are provided. The compensation method includes measurement processes of N times, N≥2. Each measurement process includes: obtaining images displayed on the display screen under different gray-scale signals, and extracting brightness of pixel points in the images; calculating difference parameters between brightness of the pixel points and brightness of the reference pixel point under the different gray-scale signals; fitting the difference parameters of the pixel points with initial brightness of the pixel points under the different gray-scale signals, to obtain initial brightness-difference parameter curves of the pixel points; calculating compensation parameters of the pixel points; during an (i)th measurement process, i=2 to N, images displayed on the display screen under the different gray-scale signals are obtained by compensating the initial brightness of the pixel points under the different gray-scale signals based on the compensation parameters obtained during an (i−1)th measurement process.
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公开(公告)号：US11436961B2
公开(公告)日：2022-09-06
申请号：US17005987
申请日：2020-08-28
Inventor： Xuehuan Feng , Yongqian Li
IPC: G06F1/26 , G09G3/3233 , G09G3/36 , G11C19/28 , G09G3/20
Abstract: A shift register and a method of driving the same, a gate driving circuit, and a display panel are disclosed. The shift register includes a display control circuit coupled to a pull-up node, a first power supply and a first control terminal respectively; a cascade output circuit coupled to a second clock terminal, the pull-up node and a cascade output terminal; a sensing control circuit coupled to the pull-up node, the cascade output terminal, a second control terminal and a third control terminal respectively; and a signal output circuit coupled to the pull-up node, a first clock terminal and a signal output terminal.
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公开(公告)号：US11410597B2
公开(公告)日：2022-08-09
申请号：US16478366
申请日：2018-12-21
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3266 , G09G3/20 , G11C19/28
Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.
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170.发明授权公开(公告)号：US11328651B2
公开(公告)日：2022-05-10
申请号：US16643966
申请日：2018-12-18
Inventor： Xuehuan Feng , Yongqian Li
Abstract: Embodiments of the present disclosure provide a shift register. The shift register includes a blank input circuit, N shift register circuits, and a compensation selection circuit. The blank input circuit is configured to store a blank input signal, and provide a blank pull-down signal to N pull-down nodes based on the blank input signal and a blank control signal. The N shift register circuits are respectively coupled to the blank input circuit via the N pull-down nodes, and are configured to output respective blank output signals based on the blank pull-down signal and respective clock signals during a blank period. The compensation selection circuit is configured to provide the blank input signal to the blank input circuit under the control of a compensation selection control signal. Herein N is a natural number greater than 1.
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