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公开(公告)号：US20210336402A1
公开(公告)日：2021-10-28
申请号：US17190141
申请日：2021-03-02
Inventor： Jonathan Ephraim David Hurwitz , Eoin E. English , Gavin P. Cosgrave
Abstract: The present disclosure relates to a laser system/package that is configured to enable the detection of a change in an optical device that is intended to alter light emitted from the laser. The system is designed to measure an electric or magnetic field that is affected by the optical device. As a result, changes in the optical device, for example because the optical device has been damaged or dislodged or removed, should be detected by a corresponding change in the electric or magnetic field.
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公开(公告)号：US20210327634A1
公开(公告)日：2021-10-21
申请号：US16851880
申请日：2020-04-17
Inventor： Xinyu Liang , Jonathan Paolucci , Leonard Shtargot
Abstract: A space efficient planar transformer can include a coupled inductor circuit that can include a metallic core, a first planar winding comprising a conductive coil having an electrical path encircling a first post of the metallic core, and a second planar winding configured to magnetically couple with the first winding via the metallic core. The second planar winding can have multiple portions. A portion of the second winding can include a first sub-portion comprising a single U-shaped planar conductive trace wrapped about the first post and a second sub-portion comprising a single U-shaped planar conductive trace wrapped about the first post. A layout of the first sub-portion can be oriented opposite a layout of the second sub-portion.
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163.发明授权公开(公告)号：US11150300B2
公开(公告)日：2021-10-19
申请号：US16715961
申请日：2019-12-16
Inventor： Brian K. Jadus , Steven John Tanghe , Deepak Gunasekaran , Michael Collins
IPC: G01R31/327 , G01R31/26 , G01R19/165 , H02H7/12
Abstract: An electronic circuit comprises a power switch circuit and a fault detection circuit. The power switch circuit includes a transistor. The fault detection circuit includes a first comparator circuit configured to compare a monitored voltage of the transistor to a detection threshold voltage and produce an indication of a circuit fault according to the comparing, and a delay circuit configured to delay the comparing by the first comparator circuit according to slew rate of the monitored voltage.
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公开(公告)号：US20210313981A1
公开(公告)日：2021-10-07
申请号：US16841132
申请日：2020-04-06
Inventor： Dennis A. Dempsey , James Thomas Sheeran
IPC: H03K17/687
Abstract: A closed loop switch control system and a corresponding method is provided for controlling an impedance of a switch. The switch, which usually comprises a transistor switch, may be part of an external circuit. The system comprises the switch and a control unit coupled to the switch. The control unit is configured to regulate an impedance of the switch to a reference impedance while also enabling a fast switch response time. This is achieved by configuring the control unit to have a frequency response comprising a plurality of dominant poles and at least one zero.
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165.发明授权公开(公告)号：US11125784B2
公开(公告)日：2021-09-21
申请号：US16007551
申请日：2018-06-13
Inventor： Jonathan Ephraim David Hurwitz
Abstract: The response of a Rogowski coil based current measuring circuit is often proportional to frequency. To correct for this a low pass or integrating function is applied to the response to linearize it. The low pass filter is made from real resistors and capacitors, and tolerances in their values significantly affect the estimate of current. This disclosure relates to a way of addressing such problems. This allows consumers of electricity to have confidence in the accuracy of, for example, their electricity meter.
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Patent Agency Ranking
公开(公告)号：US20210286748A1
公开(公告)日：2021-09-16
申请号：US17193451
申请日：2021-03-05
Inventor： Michal Brychta , Brian Paul Murray , Jacobo Riesco-Prieto
Abstract: Disclosed are embodiments that provide digital data communication between a single-pair Ethernet and a multi-pair Ethernet. Some embodiments include a single-pair Ethernet interface that is configured to operate in at least two modes. In a first mode, the single-pair Ethernet interface operates in a conventional manner. In a second mode, alternate pin configurations are employed to provide a low-cost interoperability between a single-pair Ethernet interface and a multi-pair Ethernet interface. For example, in the second mode, the single-pair Ethernet receives, via a first receive data pin, from a first transmit data pin of the multi-pair Ethernet interface, a data signal, and receives, via a second receive data pin, from a second transmit data pin of the multi-pair Ethernet interface, a second data signal.
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公开(公告)号：US20210281676A1
公开(公告)日：2021-09-09
申请号：US16828381
申请日：2020-03-24
Inventor： Xiangzhi WU , Hsien-Chieh LIU
IPC: H04M1/725 , H03K17/955
Abstract: Disclosed herein are proximity detection sensor arrangements, as well as related methods and devices. In some embodiments, a sensor arrangement in an electronic device may include a first circuit layer including a proximity pad and a first reference pad, and a second circuit layer including a second reference pad and a temperature pad. The first circuit layer may be between the second circuit layer and a user-facing surface of the electronic device, the first reference pad may be electrically coupled to the second reference pad, and the first reference pad may be between the temperature pad and the user-facing surface.
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公开(公告)号：US11105843B2
公开(公告)日：2021-08-31
申请号：US16598962
申请日：2019-10-10
Inventor： Amit Kumar Singh , Christopher C. McQuilkin
Abstract: A stabilization technique is disclosed that suppresses or inhibits glitching behavior on automated test equipment (ATE) during mode transitions. Adjustable stabilizing circuitry can be coupled to at least one of a force voltage circuit or a force current circuit is forcing voltage or current to a device under test (DUT). The adjustable stabilizing circuitry can be adjustably configurable in response to whether at least one of a current clamp or a voltage clamp is in an active clamping mode. In this manner, unwanted glitching behavior associated with mode changes can be reduced or suppressed.
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公开(公告)号：US20210265956A1
公开(公告)日：2021-08-26
申请号：US17316661
申请日：2021-05-10
Inventor： Bernhard STRZALKOWSKI
Abstract: Herein disclosed in some embodiments is a fault detector for power amplifiers of a communication system. The fault detector can detect a portion of the power amplifiers that are in fault condition and can prevent or limit current flow to the power amplifiers in fault condition while allowing the rest of the power amplifiers to operate normally. The fault detector can further indicate which power amplifiers are in fault condition and/or the cause for the power amplifiers to be in fault condition. Based on the indication, a controller can direct communications away from the power amplifiers in fault condition and/or perform operations to correct the fault condition.
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公开(公告)号：US20210265281A1
公开(公告)日：2021-08-26
申请号：US16801093
申请日：2020-02-25
Inventor： Padraig Fitzgerald , George Redfield Spalding, JR. , Jonathan Ephraim David Hurwitz , Michael J. Flynn
IPC: H01L23/00 , H01L23/528 , H01L27/06 , H01L21/8234 , H01L21/306
Abstract: The present disclosure relates to integrated circuits which include various structural elements designed to reduce the impact of strain on the electronic components of the circuit. In particular, a combination of trenches and cavities are used to mechanically isolate the integrated circuit from the surrounding substrate. The trenches may be formed such that they surround the integrated circuit, and the cavities may be formed under the integrated circuit. As such, the integrated circuit may be formed on a portion of the substrate that forms a platform. In order that the platform does not move, it may be tethered to the surrounding substrate. By including such mechanical elements, variation in the electrical characteristics of the integrated circuit are reduced.
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