公开(公告)号：US20230154984A1

公开(公告)日：2023-05-18

申请号：US17742943

申请日：2022-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Tai-Jung Kuo ,  Sung-En Lin ,  Zhen-Cheng Wu ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742

Abstract: In an embodiment, a device includes: first source/drain regions; a first insulating fin between the first source/drain regions, the first insulating fin including a first lower insulating layer and a first upper insulating layer; second source/drain regions; and a second insulating fin between the second source/drain regions, the second insulating fin including a second lower insulating layer and a second upper insulating layer, the first lower insulating layer and the second lower insulating layer including the same dielectric material, the first upper insulating layer and the second upper insulating layer including different dielectric materials.

公开(公告)号：US20230138136A1

公开(公告)日：2023-05-04

申请号：US17717839

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shao Li ,  Shu-Han Chen ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

Abstract: A method of forming a nanostructure field-effect transistor (nano-FET) device includes: forming a fin structure that includes a fin and alternating layers of a first semiconductor material and a second semiconductor material overlying the fin; forming a dummy gate structure over the fin structure; forming source/drain regions over the fin structure on opposing sides of the dummy gate structure; removing the dummy gate structure to expose the first and second semiconductor materials under the dummy gate structure; selectively removing the exposed first semiconductor material, where after the selectively removing, the exposed second semiconductor material remains to form nanostructures, where different surfaces of the nanostructures have different atomic densities of the second semiconductor material; forming a gate dielectric layer around the nanostructures, thicknesses of the gate dielectric layer on the different surfaces of the nanostructures being formed substantially the same; and forming a gate electrode around the gate dielectric layer.

公开(公告)号：US11640977B2

公开(公告)日：2023-05-02

申请号：US17026976

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Ho Lin ,  Chun-Heng Chen ,  Xiong-Fei Yu ,  Chi On Chui

IPC: H01L21/76 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode.

公开(公告)号：US20230117889A1

公开(公告)日：2023-04-20

申请号：US17659700

申请日：2022-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ru Lin ,  Shu-Han Chen ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure includes forming alternating first semiconductor layers and second semiconductor layers stacked over a substrate. The method also includes etching the first semiconductor layers and the second semiconductor layers to form a fin structure. The method also includes oxidizing the first semiconductor layers to form first oxidized portions of the first semiconductor layers and oxidizing the second semiconductor layers to form second oxidized portions of the second semiconductor layers. The method also includes removing the oxides over the sidewalls of the second semiconductor layers. After removing the second oxidized portions, an upper layer of the second semiconductor layers is narrower than a lower layer of the second semiconductor layers. The method also includes removing the first semiconductor layers to form a gate opening between the second semiconductor layers. The method also includes forming a gate structure in the gate opening.

公开(公告)号：US11631698B2

公开(公告)日：2023-04-18

申请号：US17070536

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/11585 ,  H01L27/11578 ,  H01L27/11592 ,  H01L27/1159

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

公开(公告)号：US20230114191A1

公开(公告)日：2023-04-13

申请号：US17651677

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234

Abstract: A method includes forming a first dummy gate stack on a protruding semiconductor fin, etching the first dummy gate stack to form a trench, extending the trench downwardly to penetrate through a portion of the protruding semiconductor fin, and filling the trench with a dielectric material to form a fin isolation region. A seam is formed in the fin isolation region, and the seam extends to a level lower than a top surface level of the protruding semiconductor fin. The seam has a top width smaller than about 1 nm. A second dummy gate stack on the protruding semiconductor fin is replaced with a replacement gate stack.

公开(公告)号：US11610841B2

公开(公告)日：2023-03-21

申请号：US16722630

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Kai-Hsuan Lee ,  Yen-Ming Chen ,  Chi On Chui ,  Sai-Hooi Yeong

IPC: H01L21/288 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/3105 ,  C23C14/02 ,  C23C14/04 ,  C23C14/06 ,  C23C16/02 ,  C23C16/04 ,  C23C16/34 ,  H01L21/02 ,  H01L23/532 ,  H01L21/32

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

公开(公告)号：US20230069187A1

公开(公告)日：2023-03-02

申请号：US17412967

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hao Hou ,  Che-Hao Chang ,  Da-Yuan Lee ,  Chi On Chui

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092

Abstract: A method includes depositing a first high-k dielectric layer over a first semiconductor region, performing a first annealing process on the first high-k dielectric layer, depositing a second high-k dielectric layer over the first high-k dielectric layer; and performing a second annealing process on the first high-k dielectric layer and the second high-k dielectric layer.

公开(公告)号：US20230040843A1

公开(公告)日：2023-02-09

申请号：US17716514

申请日：2022-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Ming Lung ,  Che-Hao Chang ,  Zhen-Cheng Wu ,  Chi On Chui

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L21/265 ,  H01L21/764 ,  H01L21/8238 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure includes a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed at a bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer over the seed layer at the bottom of the opening; and selectively growing a source/drain material on opposing sidewalls of the second semiconductor material exposed by the opening.

公开(公告)号：US20230008998A1

公开(公告)日：2023-01-12

申请号：US17567269

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi On Chui ,  Sheng-Chen Wang

IPC: H01L27/11597 ,  H01L27/11514 ,  G11C5/06 ,  H01L29/78 ,  H01L29/66

Abstract: In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.