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公开(公告)号：US20180233082A1
公开(公告)日：2018-08-16
申请号：US15757786
申请日：2015-08-14
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Longyan Wang , Yongqian Li
IPC: G09G3/3233 , G09G3/3258
CPC classification number: G09G3/3233 , G09G3/3258 , G09G2300/0426 , G09G2300/0819 , G09G2300/0838 , G09G2300/0842 , G09G2300/0885 , G09G2320/043
Abstract: The present disclosure provides a compensating circuit. The compensating circuit includes a feedback module (101), and a driving transistor with a first gate, a second gate, a first electrode, and a second electrode. A first terminal of the feedback module (101) is connected to a first voltage source and a second terminal of the feedback module (101) is connected to the first electrode and the second gate of the driving transistor; and the first gate of the driving transistor is connected to a data line, and the second electrode of the driving transistor for outputting a driving current.
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公开(公告)号：US20250151583A1
公开(公告)日：2025-05-08
申请号：US19014454
申请日：2025-01-09
Inventor： Pan Xu , Zhidong Yuan , Yongqian Li , Can Yuan
IPC: H10K59/80 , H10K59/12 , H10K59/124
Abstract: Provided are a display panel and a method for manufacturing the same, and a display device. The display panel includes: a base substrate including a display area and a peripheral area; a separator located at the peripheral area and including at least one separation portion, each separation portion including a first and a second separation layer, and the orthographic projection of the first separation layer on the base substrate is within that of the second separation layer; a cathode including: a first cathode portion, and a second cathode spaced apart from the first cathode portion; and an encapsulation layer including a first and a second inorganic layer, and an organic layer located between the first and the second inorganic layer, wherein edges of the orthographic projections of the first inorganic layer, the organic layer, and the second inorganic layer on the base substrate overlap.
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公开(公告)号：US20250078768A1
公开(公告)日：2025-03-06
申请号：US18703506
申请日：2023-08-31
Applicant: Hefei BOE Joint Technology Co., Ltd. , BOE Technology Group Co., Ltd. , Beijing BOE Technology Development Co., Ltd.
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
Abstract: A shift register unit, a display driving circuit, a display panel, and a control method. The shift register unit includes: an input circuit configured to provide signals of an input signal terminal (IN) and a power signal terminal (VGH) to first and second pull-up nodes (Q1, Q2); a first control circuit configured to control potentials of the first pull-down node (QB1), and the first pull-up node (Q1); a second control circuit configured to control potentials of the second pull-up node (Q2) and the second pull-down node (QB2) based on the first pull-up node (Q1) and the first pull-down node (QB1); and an output circuit configured to provide the signal of one of the power signal terminal (VGH) and the reference signal terminal (VGL) to an output signal terminal (OUT) under control of the second pull-up node (Q2) and the second pull-down node (QB2).
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公开(公告)号：US12217696B2
公开(公告)日：2025-02-04
申请号：US17914047
申请日：2021-11-09
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3266 , G09G3/32 , G11C19/28
Abstract: A scan driving circuit includes shift registers and clock signal lines. A shift register includes: an output circuit electrically connected to a scan input signal terminal and a pull-up node; a black frame insertion circuit electrically connected to a first clock signal terminal, a black frame insertion input signal terminal, a first voltage signal terminal, a second clock signal terminal and the pull-up node; and an output circuit electrically connected to the pull-up node, a third clock signal terminal, a shift signal terminal, a fourth clock signal terminal and a first output signal terminal. The shift registers include first shift registers and second shift registers. Third and fourth clock signal terminals of a first shift register are electrically connected to a same clock signal line. Third and fourth clock signal terminals of a second shift register are electrically connected to different clock signal lines.
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公开(公告)号：US12217678B2
公开(公告)日：2025-02-04
申请号：US18257521
申请日：2022-04-27
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3233 , H10K59/121 , H10K59/131
Abstract: A display substrate includes a plurality of pixel circuits, and the pixel circuits each include a sensing circuit and a light-emitting control circuit. In a second direction, adjacent three rows of pixel circuits are a first row of pixel circuits, a second row of pixel circuits and a third row of pixel circuits. A region between the first row of pixel circuits and the second row of pixel circuits is a first gap region. In the first row of pixel circuits and the second row of pixel circuits, a sensing circuit of each pixel circuit is closer to the first gap region than a light-emitting control circuit of the pixel circuit, and sensing signal terminals of sensing circuits of two pixel circuits in a same column are a same signal terminal.
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Patent Agency Ranking
公开(公告)号：US12200989B2
公开(公告)日：2025-01-14
申请号：US17630171
申请日：2021-04-12
Inventor： Yongqian Li , Zhenhua Qiu , Ying Wang , Meng Li , Dongxu Han , Dacheng Zhang , Shi Sun
IPC: H10K59/131 , H10K50/86 , H10K59/12 , H10K59/121 , H10K71/00
Abstract: Provided in the present disclosure are a display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises a plurality of display units, each display unit comprising a display area and a transparent area, and the display area comprising a plurality of sub-pixels; each sub-pixel comprises a second metal layer and a third metal layer, the second metal layer comprising a first scanning line and a second scanning line defining a display row, the third metal layer comprising a first power source line, a second power source line, a compensation line, and a data line defining the plurality of sub-pixels; the first power source line, the second power source line, the compensation line, and the data line all comprise a vertical linear section and a horizontal polyline section.
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147.发明授权公开(公告)号：US12183237B2
公开(公告)日：2024-12-31
申请号：US18452552
申请日：2023-08-20
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3266 , G09G3/20 , G11C19/28
Abstract: A shift-register unit circuit includes a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node; an output sub-circuit configured to output signal under control of the first node; a first control sub-circuit, configured to control a voltage level of a second node under control of the first node; a second control sub-circuit configured to pull down voltage levels of the first node and the output terminal to turn-off voltage levels under control of the second node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point.
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公开(公告)号：US20240404444A1
公开(公告)日：2024-12-05
申请号：US18797976
申请日：2024-08-08
Inventor： Xuehuan Feng , Yongqian Li
Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output an output blanking output control signal; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal; a selection sub-circuit, having a first terminal connected to the second input sub-circuit, a second terminal connected to the first input sub-circuit, and a third terminal connected to a first node, configured to control a potential of the first node according to the display output control signal and the blanking output control signal; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node.
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公开(公告)号：US12022713B2
公开(公告)日：2024-06-25
申请号：US17731874
申请日：2022-04-28
Inventor： Can Yuan , Yongqian Li , Zhidong Yuan , Meng Li
IPC: H01L29/08 , G09G3/00 , H10K59/121 , H10K59/131 , H10K59/35
CPC classification number: H10K59/353 , G09G3/00 , G09G3/006 , H10K59/1213 , H10K59/1216 , H10K59/131
Abstract: An array substrate and a detection method thereof, and a display panel are disclosed. The array substrate includes a plurality of subpixels and a plurality of signal line structures. The plurality of subpixels are arranged in an array of a plurality of rows and a plurality of columns along a first direction and a second direction. Each signal line structure of the plurality of signal line structures includes at least one first detection line extending along the first direction; adjacent (n)th row and (n+1)th row of subpixels in the array form a subpixel row group, and the signal line structure is configured to be connected to the (n)th row and (n+1)th row of subpixels and detect electrical characteristics of first transistors or light-emitting elements in the subpixels.
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公开(公告)号：US11967620B2
公开(公告)日：2024-04-23
申请号：US17682239
申请日：2022-02-28
Applicant: BOE Technology Group Co., Ltd.
Inventor： Pan Xu , Yicheng Lin , Cuili Gai , Ling Wang , Yongqian Li
IPC: H01L29/417 , H01L27/12 , H01L29/66 , H01L29/786 , H10K59/121 , H10K59/126 , H10K59/131 , H01L21/44
CPC classification number: H01L29/41733 , H01L27/127 , H01L29/66969 , H01L29/78618 , H01L29/78633 , H10K59/1216 , H10K59/126 , H10K59/131 , H01L21/44 , H01L29/7869
Abstract: Embodiments of the present disclosure provide a thin film transistor, a method of manufacturing the same, and a display device. The thin film transistor includes a metal conductive pattern layer, an interlayer insulating layer, and a metal oxide layer; and the metal conductive pattern layer includes: a light shielding pattern, a source signal line, and/or a drain signal line; the metal oxide layer includes: a source electrode, a drain electrode, and an active layer. An orthographic projection of the active layer on the base substrate has an overlapping region with that of the light shielding pattern; the source electrode extends through the interlayer insulating layer to connect to the source signal line, and/or the drain electrode extends through the interlayer insulating layer to connect to the drain signal line.
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