Abstract:
The present invention relates to an output driver circuit for a semiconductor memory device, in particular, a memory device using a DDR II concept or a concept similar thereto, which can reduce a variation in the slew rate of an output driver thereof between maximum and minimum values, while satisfying requirements of characteristics associated with slew rate.
Abstract:
In a display apparatus, a housing unit includes a front case having an opening and a rear case being coupled to the front case. In some embodiments, a receiving container is in the housing unit, and includes a sidewall having a first fixture portion protruded from the sidewall and extended toward an inner side face of the housing unit. A display panel is positioned in the housing unit, and has a display area corresponding to the opening. In some embodiments, a chassis includes a first chassis portion and a second chassis portion. A first chassis portion is on an edge portion of the display panel. A second chassis portion includes a second fixture portion extended from the first chassis portion along a sidewall of the receiving container, and the second fixture portion is protruded toward the inner side face of the housing unit. The display apparatus may have a compact size.
Abstract:
A line light source includes an illuminating bar having end portions opposite each other, and a light emitting diode disposed on each end portion of the illuminating bar. The end portions of the illuminating bar are each slant with respect to a vertical axis thereof at a predetermined slant angle. The illuminating bar includes a fluorescent material or a phosphorescent material.
Abstract:
A display device is provided. The display device includes a main display panel, a sub-display panel, and a plurality of lamps simultaneously supplying light to the first and second display panels; an openness sensing unit in which an output signal is defined based on a degree of openness of the display device; and a lamp controlling unit selecting one of the display panels based on the output signal from the openness sensing unit and defining the number of lamps to be turned on based on the selected display panel, and supplying the light to the main and sub-display panels by lighting the defined number of lamps. In one embodiment, the display device is a display device for a mobile phone, and the lamps are light emitting diodes. Accordingly, the number of lamps to be turned on is varied based on the selected display panel, and consumption power therefore decreases.
Abstract:
In a two-way backlight assembly and a two-way LCD apparatus, the two-way backlight assembly provides light emitted from one light source to a first direction where a main LCD panel is placed and to a second direction where a sub LCD panel is placed. Also, a sub mold part for receiving the sub LCD panel comprises a black-colored material so as to prevent reflection of the light. Accordingly, thickness and power consumption of the backlight assembly may be reduced and display quality may be also improved by preventing leakage of the light at ends of the sub LCD panel.
Abstract:
A write path scheme in a synchronous DRAM having: a data converter unit to convert serial input data to parallel output data, a multiplexer to output data from the data converter unit depending on a first mode selection signal and a second mode selection signal, and a data input/output sense amplifier having a plurality of sense amplifiers to separately operate the plurality of sense amplifiers depending on the first mode selection signal and the second mode selection signal to sense data from the multiplexer and then load the data on a global input/output line. Also included is a write driver to load data from the global input/output line on a local input/output line.
Abstract:
A semiconductor memory device having a plurality of banks for stably performing a write with auto-prechrage (WRA) command or a read with auto-precharge (RDA) command, including: a bank signal generation unit for generating an interrupt bank signal based on a bank address signal and a column address strobe (CAS) signal; a data access period detection unit for generating a data access period signal based on the CAS signal and a bit line disable signal; and a masking signal generation unit for generating a masking signal in order to controlling a logic level of an auto-precharge signal based on the data access period signal and the interrupt bank signal.
Abstract:
A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.
Abstract:
Methods, systems and computer program products that may improve the efficiency of the video encoding process. Mode decision processing and bit stream packing may be performed in parallel for various frames in a sequence. This reduces the amount of idle time for both the mode decision processing logic and the bit stream packing logic, improving the overall efficiency of the video encoder.
Abstract:
Systems, devices and methods are described including determining an inter-view coding mode for at least a portion of an image frame, specifying a corresponding value of an inter-view coding mode indicator, and providing the mode indicator in a bitstream that includes an encoded motion vector associated with the image frame portion. A first value of the mode indicator corresponds to a first inter-view coding mode where the encoded motion vector includes components in multiple dimensions. A second value of the mode indicator corresponds to a second inter-view coding mode where the encoded motion vector components include components in only one dimension.