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公开(公告)号：US10749572B2
公开(公告)日：2020-08-18
申请号：US16277678
申请日：2019-02-15
Inventor： Gwenael Maillet , Jean-Louis Labyre , Gilles Bas
Abstract: A circuit includes a near-field communication circuit configured to receive a radio frequency control signal transmitted in a near-field regime, a pulse width modulation signal generation circuit coupled to the near-field communication circuit circuit and configured to generate a pulse width modulation signal according to the radio frequency control signal, and a non-volatile memory coupled to both the near-field communication circuit circuit and the pulse width modulation signal generation circuit, the non-volatile memory comprising digital words for configuring the pulse width modulation signal.
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132.发明授权公开(公告)号：US10732894B2
公开(公告)日：2020-08-04
申请号：US15900481
申请日：2018-02-20
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
Abstract: A method of writing in a memory of the EEPROM type includes, in the presence of a string of new bytes to be written in the memory plane in at least one destination memory word already containing old bytes, a verification for each destination memory word whether or not the old bytes of this destination memory word must all be replaced with new bytes. The method also includes a reading of the old bytes of this destination memory word only if the old bytes must not all be replaced with new bytes.
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133.发明授权公开(公告)号：US10727239B2
公开(公告)日：2020-07-28
申请号：US16130593
申请日：2018-09-13
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet
IPC: H01L27/11517 , H01L29/423 , G11C7/18 , H01L29/66 , G11C16/04 , H01L21/28 , H01L27/11524 , H01L29/788 , G11C16/08 , G11C16/24
Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.
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公开(公告)号：US10705838B2
公开(公告)日：2020-07-07
申请号：US15607615
申请日：2017-05-29
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Vincent Onde
Abstract: Microcode is stored in a program memory and intended to be executed by a central processing unit of a processing unit. The processing unit may include a memory controller associated with each program memory and a hardware peripheral. The method includes, in response to a request to update the microcode, a transmission, to each hardware peripheral, of a global authorization request signal obtained from an elementary authorization request signal generated by each corresponding memory controller, a transmission of a global authorization signal obtained from an elementary authorization signal generated by each hardware peripheral in response to the global authorization request signal and after satisfying a predetermined elementary condition, and an updating of each microcode by the corresponding memory controller only after the global authorization signal is received.
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公开(公告)号：US10672644B2
公开(公告)日：2020-06-02
申请号：US15992481
申请日：2018-05-30
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Franck Julien
IPC: H01L29/06 , H01L21/762 , H01L21/02 , H01L21/311 , H01L21/84 , H01L21/8238 , H01L27/12 , H01L27/092 , H01L21/3105 , H01L21/28 , H01L29/66
Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.
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Patent Agency Ranking
公开(公告)号：US10664735B2
公开(公告)日：2020-05-26
申请号：US16277698
申请日：2019-02-15
Inventor： Gwenael Maillet , Jean-Louis Labyre , Gilles Bas
Abstract: A method of reducing noise generated by pulse width modulation (PWM) signals includes generating a PWM pulse train using a first set of parameter values and modifying the PWM pulse train during a near-field communication so that the PWM pulse train is generated using a second set of parameter values. Modifying the PWM pulse train includes reducing at least one parameter value of the first set of parameter values. The method further includes resuming generation of the PWM pulse train using the first set of parameter values after the near-field communication.
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公开(公告)号：US10659020B2
公开(公告)日：2020-05-19
申请号：US16271077
申请日：2019-02-08
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jean Nicolai , Albert Martinez
Abstract: A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.
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公开(公告)号：US10560089B2
公开(公告)日：2020-02-11
申请号：US16161531
申请日：2018-10-16
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Nicolas Borrel , Jimmy Fort , Francesco La Rosa
Abstract: A power supply voltage is monitored by a monitoring circuit including a band gap voltage generator core including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the band gap voltage generator core generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.
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公开(公告)号：US10552365B2
公开(公告)日：2020-02-04
申请号：US15902473
申请日：2018-02-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Chama Ameziane El Hassani
Abstract: In some embodiments, a buffer stage device includes a data input for receiving a data signal, a clock input for receiving a clock signal, a data output and a processor that is configured to deliver, to the data output, the data from the data signal in synchronism with clock cycles of the clock signal. The processor includes a first buffer module configured to deliver, to the data output, each datum in synchronism with a first edge of the clock signal and during a first half of a clock cycle, and a second buffer module configured to hold the datum at the data output during the second half of the clock cycle.
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公开(公告)号：US20200035671A1
公开(公告)日：2020-01-30
申请号：US16518436
申请日：2019-07-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Pascal Fornara , Fabrice Marinet
IPC: H01L27/02 , H01L23/525
Abstract: An integrated circuit includes a circuit module storing sensitive data. An electrically conductive body at a floating potential is located in the integrated circuit and holds an initial amount of electric charge. In response to an attack attempting to access the sensitive data, electric charge is collected on the electrically conductive body. A protection circuit is configured to ground an output of the circuit module, and thus preclude access to the sensitive data, in response to collected amount of electric charge on the electrically conductive body differing from the initial amount and exceeding a threshold.
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