公开(公告)号：US20200052724A1

公开(公告)日：2020-02-13

申请号：US16658270

申请日：2019-10-21

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM

IPC: H03M13/27 ,  H03M13/11 ,  H04L1/00 ,  H03M13/25 ,  H03M13/29 ,  H03M13/15

Abstract: A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

公开(公告)号：US20190393891A1

公开(公告)日：2019-12-26

申请号：US16559329

申请日：2019-09-03

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik PARK ,  Heung-Mook KIM ,  Sun-Hyoung KWON ,  Nam-Ho HUR

IPC: H03M13/11 ,  H04L1/00 ,  H03M13/03 ,  H03M13/00

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

公开(公告)号：US20190356340A1

公开(公告)日：2019-11-21

申请号：US16530758

申请日：2019-08-02

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Bo-Mi LIM ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

IPC: H03M13/27 ,  G06F11/10 ,  H03M13/11 ,  H04L1/00 ,  H03M13/00 ,  H03M13/25

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

公开(公告)号：US20190356338A1

公开(公告)日：2019-11-21

申请号：US16527485

申请日：2019-07-31

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

IPC: H03M13/27 ,  H03M13/25 ,  H03M13/11 ,  H04L1/00

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

公开(公告)号：US20190341940A1

公开(公告)日：2019-11-07

申请号：US16516514

申请日：2019-07-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Bo-Mi LIM ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

IPC: H03M13/27 ,  H03M13/25 ,  H04L1/00 ,  H03M13/11

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

公开(公告)号：US20190305997A1

公开(公告)日：2019-10-03

申请号：US16442780

申请日：2019-06-17

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae-Young LEE ,  Sung-Ik PARK ,  Sun-Hyoung KWON ,  Heung-Mook KIM

IPC: H04L27/26 ,  H04L1/00 ,  H04W52/34 ,  H04L5/00 ,  H04L27/18

Abstract: An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling, type information of Physical Layer Pipes (PLPs) and time interleaver information shared by the core layer signal and the enhanced layer signal.

公开(公告)号：US20190296841A1

公开(公告)日：2019-09-26

申请号：US16436621

申请日：2019-06-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

IPC: H04H20/42 ,  H04L1/00 ,  H04L27/26 ,  H04H60/07 ,  H04H60/73

Abstract: An apparatus and method for generating a broadcast signal frame using enhanced layer dummy values are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and enhanced layer data corresponding to the one of the time interleaver groups include dummy values.

公开(公告)号：US20190260508A1

公开(公告)日：2019-08-22

申请号：US16401006

申请日：2019-05-01

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

IPC: H04L1/00 ,  H03M13/00 ,  H03M13/27 ,  H03M13/11 ,  H03M13/25

Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

公开(公告)号：US20190173707A1

公开(公告)日：2019-06-06

申请号：US16204813

申请日：2018-11-29

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung-Ik PARK ,  Jae-Young LEE ,  Sun-Hyoung KWON ,  Heung-Mook KIM

IPC: H04L27/26 ,  H04J11/00 ,  H04L27/34 ,  H04N21/2343 ,  H04N19/30 ,  H04L1/00 ,  H04W4/06

CPC classification number: H04L27/2615 ,  H04J11/00 ,  H04J2011/0013 ,  H04L1/0058 ,  H04L1/007 ,  H04L27/2601 ,  H04L27/2613 ,  H04L27/3488 ,  H04N19/30 ,  H04N21/234327 ,  H04W4/06 ,  Y02D70/00 ,  Y02D70/166 ,  Y02D70/168

Abstract: An apparatus and method for generating a broadcast signal frame including preamble for signaling injection level information. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes an injection level controller configured to generate a power reduced enhanced layer signal by reducing a power of an enhanced layer signal; a combiner configured to generate a multiplexed signal by combining a core layer signal and the power reduced enhanced layer signal; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling injection level information corresponding to the injection level controller.

公开(公告)号：US20190082228A1

公开(公告)日：2019-03-14

申请号：US16185457

申请日：2018-11-09

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung-Ik PARK ,  Jae-Young LEE ,  Sun-Hyoung KWON ,  Heung-Mook KIM

IPC: H04N21/61 ,  H04H20/42 ,  H04N21/2383 ,  H04L5/00 ,  H04L27/36 ,  H04W28/06 ,  H04L27/18 ,  H04L27/38

Abstract: An apparatus and method for broadcast signal frame using a bootstrap including a symbol for signaling a BICM mode and OFDM parameters of a preamble, together are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal. In this case, the bootstrap includes a symbol for signaling a BICM mode and OFDM parameters of L1-Basic of the preamble, together.