公开(公告)号：US06208010B1

公开(公告)日：2001-03-27

申请号：US08574110

申请日：1995-12-18

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L2900

CPC分类号： H01L27/10805 ,  H01L27/0214 ,  H01L27/0218 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/105 ,  Y10S257/901 ,  Y10S257/904

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US6047256A

公开(公告)日：2000-04-04

申请号：US77506

申请日：1993-06-17

申请人： Shinji Koga ,  Takao Watanabe ,  Kazunaga Yoshida

发明人： Shinji Koga ,  Takao Watanabe ,  Kazunaga Yoshida

IPC分类号： G10L11/00 ,  G10L15/02 ,  G10L15/06 ,  G10L15/14

CPC分类号： G10L15/14 ,  G10L15/063 ,  G10L15/02 ,  G10L15/142 ,  G10L2015/0631

摘要： In a system for recognizing a time sequence of feature vectors of a speech signal representative of an unknown utterance as one of a plurality of reference patterns, a generator (11) for generating the reference patterns has a converter (15) for converting a plurality of time sequences of feature vectors of an input pattern of a speech signal with variances to a plurality of time sequences of feature codes with reference to code vectors (14) which are previously prepared by the known clustering. A first pattern former (16) generates a state transition probability distribution and an occurrence probability distribution of feature codes for each state in a state transition network. A function generator (17) calculates parameters of continuous Gaussian density function from the code vectors and the occurrence probability distribution to produce the continuous Gaussian density function approximating the occurrence probability distribution. A second pattern former (18) produces a reference pattern defined by the state transition probability distribution and the continuous Gaussian density function. For a plurality of different training words, a plurality of reference patterns are generated and are memorized in the reference pattern generator.

摘要翻译： 在用于识别表示作为多个参考图案之一的未知发音的语音信号的特征向量的时间序列的系统中，用于生成参考图案的发生器（11）具有转换器（15），用于将多个 参考由先前由已知聚类准备的代码矢量（14），语音信号的输入模式的特征向量的时间序列具有方差与特征码的多个时间序列的方差。 第一图案形成器（16）在状态转换网络中产生状态转移概率分布和每个状态的特征码的发生概率分布。 函数发生器（17）从码矢量和出现概率分布计算连续高斯密度函数的参数，以产生接近发生概率分布的连续高斯密度函数。 第二模式形成器（18）产生由状态转移概率分布和连续高斯密度函数定义的参考模式。 对于多个不同的训练词，生成多个参考图案并将其存储在参考图案生成器中。

公开(公告)号：US5854636A

公开(公告)日：1998-12-29

申请号：US931776

申请日：1997-09-16

申请人： Takao Watanabe ,  Yoshinobu Nakagome ,  Kazuo Ishikura ,  Tetsuya Nakagawa ,  Atsushi Kiuchi

发明人： Takao Watanabe ,  Yoshinobu Nakagome ,  Kazuo Ishikura ,  Tetsuya Nakagawa ,  Atsushi Kiuchi

IPC分类号： G06T1/20 ,  G06F13/00 ,  G06F15/167 ,  G06F15/80 ,  G06F17/10 ,  G06F17/15 ,  G06T5/20 ,  G11C7/10

CPC分类号： G11C7/1006 ,  G06F17/10 ,  G06F17/15

摘要： A semiconductor integrated circuit having a two-dimensional array (MAR) and a parallel data transfer circuit (TRC) for transferring from the array data read out in parallel through data lines, in parallel to a processing circuit group (PE) by selecting the word lines of the two-dimensional memory array. The processing circuit group executing processing operations in parallel by using the data transferred from the parallel data transfer circuit. Each of the processing circuits having access to a plurality of series word lines and the data lines of the two-dimensional array through the parallel data transfer circuits. The arrangement of the parallel data transfer circuits allowing for an overlap range wherein data from each of the data lines of the memory array is available to more than one of the parallel data transfer circuits. Since the data lines of the two-dimensional memory array have the overlapped range, convolution processing operations or the like can be executed in parallel for the two-dimensional data stored in the two-dimensional memory array in a high parallelism and at a high speed.

摘要翻译： 一种具有二维阵列（MAR）和并行数据传输电路（TRC）的半导体集成电路，用于从通过数据线并行读出的阵列数据并行地传送到处理电路组（PE），通过选择字 二维存储器阵列的行。 处理电路组通过使用从并行数据传送电路传送的数据并行地执行处理操作。 每个处理电路可以通过并行数据传输电路访问多个串行字线和二维阵列的数据线。 并行数据传输电路的布置允许重叠范围，其中来自存储器阵列的每条数据线的数据可用于多于一个并行数据传输电路。 由于二维存储器阵列的数据线具有重叠范围，因此可以以高并行性和高速度对存储在二维存储器阵列中的二维数据并行执行卷积处理操作等 。

公开(公告)号：US5657273A

公开(公告)日：1997-08-12

申请号：US558778

申请日：1995-11-15

申请人： Kazushige Ayukawa ,  Takao Watanabe ,  Yoshinobu Nakagome

发明人： Kazushige Ayukawa ,  Takao Watanabe ,  Yoshinobu Nakagome

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C8/16

CPC分类号： G11C7/1006 ,  G11C7/10 ,  G11C8/16

摘要： A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The device is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished. The device is also capable of processing data on once-activated word lines successively thereby reducing the number of times each word line is driven so that the power consumption is reduced.

摘要翻译： 集成在芯片上的半导体器件包括存储单元阵列，多个处理元件和多个数据传输电路，其通过分别提供的读取路径和写入路径在存储器单元和处理元件之间传送数据。 该装置能够分别将数据从存储器单元传送到处理元件，并且从处理元件到存储器单元同时通过读取路径和写入路径，从而实现更快的图像数据处理。 该装置还能够连续地处理一次激活的字线上的数据，从而减少每个字线被驱动的次数，从而降低功耗。

公开(公告)号：US5594916A

公开(公告)日：1997-01-14

申请号：US369163

申请日：1995-01-04

申请人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

发明人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC分类号： G06F15/18 ,  G06F17/16 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00 ,  G06F9/00

CPC分类号： G06N3/063

摘要： A data processing system has a memory for realizing large-scale and high-speed parallel distributed processing and, especially, a data processing system for neural network processing. The neural network processing system comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operation of the memory circuit, the input/output circuit and the processing circuit. The processing circuit includes at least one of an address, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neuron output values such as the product of sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neurons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

摘要翻译： 数据处理系统具有用于实现大规模高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。 神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制存储电路，输入/输出电路和处理电路的操作的控制电路。 处理电路包括地址，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以并行实现用于确定神经元输出值（例如和乘积）所必需的处理的至少一部分。 此外，这些电路在多个神经元之间共享并且以分时方式操作以确定多个神经元输出值。 此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

公开(公告)号：US5535410A

公开(公告)日：1996-07-09

申请号：US335680

申请日：1994-11-08

申请人： Takao Watanabe ,  Tetsuya Nakagawa ,  Yoshinobu Nakagome

发明人： Takao Watanabe ,  Tetsuya Nakagawa ,  Yoshinobu Nakagome

IPC分类号： G06F15/16 ,  G06F9/318 ,  G06F9/38 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F9/3889 ,  G06F15/8023 ,  G06F9/30189 ,  G06F9/3885 ,  G06F9/3887 ,  G06T15/005

摘要： A parallel processor utilizing a memory cell array for rapidly performing parallel processing by switching between SIMD and MIMD operations depending on the type of problems to be solved. Where SIMD and MIMD operations are mixed in an application, the time loss in the switching therebetween is eliminated so as to enhance the speed of the processing. The parallel processor comprises a two-dimensional memory array for storing data to be operated on; a transfer network for transferring to a group of processing elements the data read in parallel from word lines connected to memory cells in the two-dimensional memory array, the group of processing elements performing parallel processing on the data transferred thereto; signal lines for transmitting an instruction in a SIMD operation mode; an instruction buffer for storing and forwarding parallelly instructions in a MIMD operation mode; and a group of switches for switching between the SIMD and the MIMD operation mode.

摘要翻译： 利用存储单元阵列的并行处理器，用于通过根据要解决的问题的类型在SIMD和MIMD操作之间切换来快速执行并行处理。 在应用中混合SIMD和MIMD操作的情况下，消除其间的切换中的时间损失，从而提高处理速度。 并行处理器包括用于存储要被操作的数据的二维存储器阵列; 传送网络，用于将连接到二维存储器阵列中的存储单元的字线并行读取的数据传送到一组处理元件，该组处理元件对传送到其上的数据执行并行处理; 用于在SIMD操作模式下发送指令的信号线; 用于以MIMD操作模式并行存储和转发指令的指令缓冲器; 以及用于在SIMD和MIMD操作模式之间切换的一组开关。

公开(公告)号：US5432886A

公开(公告)日：1995-07-11

申请号：US832600

申请日：1992-02-07

申请人： Satoshi Tsukada ,  Takao Watanabe

发明人： Satoshi Tsukada ,  Takao Watanabe

IPC分类号： G10L11/00 ,  G10L15/08 ,  G10L15/10 ,  G10L15/20 ,  G10L15/28 ,  G10L9/00

CPC分类号： G10L15/10

摘要： In a speech recognition device including a similarity calculator for calculating a usual similarity as a provisional similarity between an input pattern and prepared reference patterns, a calculating arrangement calculates a reference similarity between the input pattern and produced reference patterns. A correcting unit corrects the provisional similarity by the reference similarity into a corrected similarity. As usual, the similarity may be a dissimilarity. The prepared reference patterns may be memorized in the calcultor or be given by concatenations of primary recognition units. Preferably, the produced reference patterns are concatenations of secondary recognition units memorized in a memory.

摘要翻译： 在包括用于计算作为输入图案与准备参考图案之间的临时相似度的通常相似度的相似度计算器的语音识别装置中，计算装置计算输入图案和产生的参考图案之间的参考相似度。 校正单元将参考相似性的临时相似性校正为校正的相似度。 像往常一样，相似性可能是不相似的。 准备的参考模式可以记录在计算器中，或者由主要识别单元的级联给出。 优选地，所产生的参考图案是存储在存储器中的辅助识别单元的级联。

公开(公告)号：US5426757A

公开(公告)日：1995-06-20

申请号：US938755

申请日：1992-09-01

申请人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

发明人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC分类号： G06F15/18 ,  G06F17/16 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00 ,  G06F15/16

CPC分类号： G06N3/063

摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

摘要翻译： 这里公开了一种数据处理系统，其中封装有用于实现大规模和高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。 根据本发明的神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。 处理电路被构造为包括加法器，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以实现用于确定诸如乘积或和的中子输出值所需的处理的至少一部分 在平行下。 此外，这些电路在多个中子之间共享并且以分时方式操作以确定多个神经元输出值。 此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

公开(公告)号：US5229898A

公开(公告)日：1993-07-20

申请号：US717342

申请日：1991-06-18

申请人： Shinobu Fujisawa ,  Takao Watanabe

发明人： Shinobu Fujisawa ,  Takao Watanabe

IPC分类号： G11B15/17 ,  G11B15/675

CPC分类号： G11B15/17 ,  G11B15/67515

摘要： A control system for a magnetic tape cassette apparatus of the type requiring no movement of a transducer for the establishment of data transfer contact with the tape cassette. Inserted lengthwise in the apparatus, the tape cassette has its apertured front side oriented toward the fixed transducer. A cassette shift mechanism subsequently moves the tape cassette in its own plane into data transfer contact with the transducer. Then a pair of tape transport spindles are moved into driving engagement with the tape cassette by a tape transport shift mechanism. Both cassette shift mechanism and tape transport shift mechanism are actuated by a motor driven dual control cam under the control of a digital microprocessor controller. The controller has inputs connected to a cam position sensor which detects predetermined angular positions of the dual control cam, a cassette loading sensor which indicates whether the cassette is in the data transfer position, and a tape transport sensor which indicates whether the drive spindles are in or out of driving engagement with the cassette. Relying on digital outputs from these sensors, the controller determines the loading of the cassette in the data transfer position and the ejection of the cassette from the apparatus.

摘要翻译： 一种用于不需要移动用于建立与磁带盒的数据传送接触的换能器的类型的磁带盒装置的控制系统。 该带盒长度方向插入设备中，其带孔正面朝向固定换能器。 盒式换档机构随后将盒式磁带在其自身的平面中移动到与换能器的数据传输接触。 然后，通过带传送换档机构将一对带传送主轴移动成与带盒的驱动接合。 在数字微处理器控制器的控制下，盒式换档机构和胶带传送换档机构由电动机驱动的双控制凸轮致动。 控制器具有连接到凸轮位置传感器的输入，该凸轮位置传感器检测双控制凸轮的预定角度位置，指示磁带盒是否处于数据传送位置的盒装载传感器，以及指示驱动器主轴是否处于 或者脱离与盒式磁带的接合。 依赖于这些传感器的数字输出，控制器确定盒式磁带在数据传送位置的装载以及盒式磁带从设备中的排出。

公开(公告)号：US5150449A

公开(公告)日：1992-09-22

申请号：US688715

申请日：1991-04-23

申请人： Kazunaga Yoshida ,  Takao Watanabe

发明人： Kazunaga Yoshida ,  Takao Watanabe

IPC分类号： G06F15/18 ,  G06N3/00 ,  G06N99/00 ,  G10L11/00 ,  G10L15/02 ,  G10L15/06 ,  G10L15/08 ,  G10L15/10 ,  G10L15/16

CPC分类号： G10L15/07

摘要： A speech recognition apparatus of the speaker adaptation type operates to recognize an inputted speech pattern produced by a particular speaker by using a reference pattern produced by a voice of a standard speaker. The speech recognition apparatus is adapted to the speech of the particular speaker by converting the reference pattern into a normalized pattern by a neural network unit, internal parameters of which are modified through a learning operation using a normalized feature vector of the training pattern produced by the voice of the particular speaker and normalized on the basis of the reference pattern, so that the neural netowrk unit provides an optimum output similar to the corresponding normalized feature vector of the training pattern. In the alternative, the speech recognition apparatus operates to recognize an inputted speech pattern by converting the inputted speech pattern into a normalized speech pattern by the neural network unit, internal parameters of which are modified through a learning operation using a feature vector of the reference pattern normalized on the basis of the training pattern, so that the neural network unit provides an optimum output similar to the corresponding normalized feature vector of the reference pattern and recognizing the normalized speech pattern according to the reference pattern.