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    Highly scalable accelerator
    111.
    发明授权
    Highly scalable accelerator 有权

    公开(公告)号：US11650947B2

    公开(公告)日：2023-05-16

    申请号：US17410063

    申请日：2021-08-24

    Applicant: Intel Corporation

    Inventor： Philip R. Lantz ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Saurabh Gayen

    IPC: G06F13/364 ,  G06F13/24 ,  G06F9/50

    CPC classification number: G06F13/364 ,  G06F9/5027 ,  G06F13/24

    Abstract: Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

    NON-POSTED WRITE TRANSACTIONS FOR A COMPUTER BUS
    112.
    发明申请
    NON-POSTED WRITE TRANSACTIONS FOR A COMPUTER BUS 有权

    公开(公告)号：US20230035420A1

    公开(公告)日：2023-02-02

    申请号：US17955353

    申请日：2022-09-28

    Applicant: Intel Corporation

    Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

    IPC: G06F13/16 ,  G06F13/42

    Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

    Techniques for virtual machine transfer and resource management
    115.
    发明授权
    Techniques for virtual machine transfer and resource management 有权

    公开(公告)号：US11556363B2

    公开(公告)日：2023-01-17

    申请号：US16479395

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Sanjay Kumar ,  Philip R. Lantz ,  Kun Tian ,  Utkarsh Y. Kakaiya ,  Rajesh M. Sankaran

    IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

    Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

    Scalable interrupt virtualization for input/output devices
    116.
    发明授权
    Scalable interrupt virtualization for input/output devices 有权

    公开(公告)号：US11200183B2

    公开(公告)日：2021-12-14

    申请号：US16493148

    申请日：2017-03-31

    Applicant: INTEL CORPORATION

    Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  Utkarsh Y. Kakaiya ,  Kun Tian

    IPC: G06F13/28 ,  G06F13/24 ,  G06F9/455 ,  G06F9/48

    Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.

    TECHNOLOGIES FOR INCREASING LINK EFFICIENCY
    117.
    发明申请
    TECHNOLOGIES FOR INCREASING LINK EFFICIENCY 有权

    公开(公告)号：US20210374087A1

    公开(公告)日：2021-12-02

    申请号：US17380712

    申请日：2021-07-20

    Applicant: Intel Corporation

    Inventor： David A. Koufaty ,  Rajesh M. Sankaran ,  Utkarsh Y. Kakaiya

    IPC: G06F13/42 ,  G06F13/40 ,  G06F9/50 ,  G06F9/54

    Abstract: Techniques for increasing link efficiency are disclosed. In one embodiment, a device handle table is created at each end of a link. Device handle allocation messages can be used to associate a particular device handle with a particular domain identifier, such as a bus/device/function (BDF) identifier or a processor address space identifier (PASID). Once a device handle is allocated, messages can be sent between the two ends of the link that include the device handle. The device handle can be used to determine the domain identifier associated with the message. As the device handle can be fewer bits than the domain identifier, the link efficiency can be increased.

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