LOGIC CELL FOR PROGRAMMABLE GATE ARRAY

    公开(公告)号:US20220376693A1

    公开(公告)日:2022-11-24

    申请号:US17529522

    申请日:2021-11-18

    摘要: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).

    Method and Apparatus for Gather/Scatter Operations in a Vector Processor

    公开(公告)号:US20220342590A1

    公开(公告)日:2022-10-27

    申请号:US17669995

    申请日:2022-02-11

    IPC分类号: G06F3/06

    摘要: In one implementation a vector processor gather/scatter apparatus comprises a plurality of vector ports, and a random access memory, where the plurality of vector ports are in communication with the random access memory, and where one or more of the plurality of vector ports uses one or more of an address register and one or more of a stride register in communication with the random access memory to allow the gather/scatter of random access memory contents.

    Method and Apparatus for Performing Convolution Neural Network Operations

    公开(公告)号:US20220300793A1

    公开(公告)日:2022-09-22

    申请号:US17480282

    申请日:2021-09-21

    摘要: A method and apparatus for performing a convolution of a N×N matrix. A weights matrix for a N×N Convolutional Neural Network (CNN) is received and is divided into 3×3 weights matrixes. Lines of image values are read and are stored in a buffer as sets of image values. A 3×3 convolution is performed to generate a 3×3 convolution value. All 3×3 convolution values associated with a particular N×N convolution and a particular set of image values are summed. The 3×3 convolutions and the summing are repeated until all columns in the set of image values have been processed; and the reading, the storing, the performing 3×3 convolutions, the summing and the repeating performing 3×3 convolutions are repeated until all lines of image values have been processed. The sums associated with a particular N×N convolution are added together to generate an N×N convolution value for each of the N×N convolutions.

    System and method for scheduling sharable PCIe endpoint devices

    公开(公告)号:US11449456B2

    公开(公告)日:2022-09-20

    申请号:US17151316

    申请日:2021-01-18

    摘要: System and method for sharing a PCIe endpoint device with a plurality of host computers, by allocating a quantum of time to a host computer of a plurality of host computers coupled to a PCIe switch, wherein the quantum of time identifies a duration of time during which the host computer has exclusive access to a shareable PCIe endpoint device coupled to the PCIe switch. Requests from the host computer are transmitted to an emulated PCIe endpoint device of the PCIe switch during the quantum of time and the requests are then redirected from the emulated PCIe endpoint device to the shareable PCIe endpoint device during the quantum of time allocated to the host computer.

    Method and Apparatus for Reading a Flash Memory Device

    公开(公告)号:US20220270698A1

    公开(公告)日:2022-08-25

    申请号:US17234993

    申请日:2021-04-20

    摘要: A method for reading a flash memory device includes storing configuration files of reliability-state Classification Neural Network (CNN) models and Regression Neural Network (RNN) inference models, and storing reliability-state tags corresponding to reliability states. The current number of P/E cycles is identified and a reliability-state CNN model is selected corresponding to the current number of P/E cycles. A neural network operation of the selected reliability-state CNN model is performed to identify a predicted reliability state. Corresponding reliability-state tags are identified and a corresponding RNN inference model is selected. A neural network operation of the selected RNN inference model is performed, using the reliability-state tags as input, to generate output indicating the shape of a threshold-voltage-shift read-error (TVS-RE) curve. Threshold Voltage Shift Offset (TVSO) values are identified corresponding to a minimum value of the TVS-RE curve and a read is performed using a threshold-voltage-shift read at the identified TVSO values.

    REDUNDANT ANGULAR POSITION SENSOR AND ASSOCIATED METHOD OF USE

    公开(公告)号:US20220136869A1

    公开(公告)日:2022-05-05

    申请号:US17146875

    申请日:2021-01-12

    发明人: Ganesh Shaga

    IPC分类号: G01D5/20 G01B7/30

    摘要: A redundant angular position sensor comprising a first angular position sensor including a first excitation coil, a first sensing coil and a second sensing coil and a second angular position sensor. The second angular position sensor including a second excitation coil, a third sensing coil and a fourth sensing coil. Each of the first, second, third and fourth sensing coils comprising a respective clockwise winding portion and a respective counter-clockwise winding portion. The redundant angular position sensor further comprises a rotatable inductive coupling element positioned in overlying relation to the sensing coils and separated from the sensing coils by a gap, wherein the rotatable inductive coupling element comprises four, substantially evenly radially spaced, sector apertures.

    Packaged semiconductor die with micro-cavity

    公开(公告)号:US11244876B2

    公开(公告)日:2022-02-08

    申请号:US16816010

    申请日:2020-03-11

    摘要: A packaged electronic die having a micro-cavity and a method for forming a packaged electronic die. The packaged electronic die includes a photoresist frame secured to the electronic die and extending completely around the device. The photoresist frame is further secured to a first major surface of a substrate so as to form an enclosure around the device. Encapsulant material extends over the electronic die and around the sides of the electronic die. The encapsulant material is in contact with the first major surface of the substrate around the entire periphery of the electronic die so as to form a seal around the electronic die.

    ANGULAR POSITION SENSOR AND ASSOCIATED METHOD OF USE

    公开(公告)号:US20220011138A1

    公开(公告)日:2022-01-13

    申请号:US16927553

    申请日:2020-07-13

    IPC分类号: G01D5/20

    摘要: An angular position sensor comprising two planar excitation coils forming a substantially circular interior area and two planar sensing coils positioned within a minor sector of the substantially circular interior area. Each of the two planar sensing coils comprises a clockwise winding portion and a counter-clockwise winding portion. The angular position sensor further comprises a substantially circular rotatable inductive coupling element positioned in overlying relation to the two planar sensing coils and separated from the two planar sensing coils by an airgap, wherein the substantially circular rotatable inductive coupling element comprises three, substantially evenly space, sector apertures.

    Error tolerant memory array and method for performing error correction in a memory array

    公开(公告)号:US11068341B2

    公开(公告)日:2021-07-20

    申请号:US16588916

    申请日:2019-09-30

    发明人: John L. McCollum

    摘要: A method for providing error correction for a memory array includes for each memory word stored in a data memory portion of the memory array having at least one bit error, storing in an error PROM error data identifying a memory address for the data word in the data memory portion, a bit position of each bit error, and correct bit data for each bit error, monitoring memory addresses presented to the data PROM, if a memory address presented to the data memory portion is an identified memory address, reading from the error PROM the bit position of each bit error and the correct bit data for each bit error, and substituting the correct bit data into each identified bit position of a sense amplifier reading data from the data memory portion.

    ERROR TOLERANT MEMORY ARRAY AND METHOD FOR PERFORMING ERROR CORRECTION IN A MEMORY ARRAY

    公开(公告)号:US20210073072A1

    公开(公告)日:2021-03-11

    申请号:US16588916

    申请日:2019-09-30

    发明人: John L. McCollum

    摘要: A method for providing error correction for a memory array includes for each memory word stored in a data memory portion of the memory array having at least one bit error, storing in an error PROM error data identifying a memory address for the data word in the data memory portion, a bit position of each bit error, and correct bit data for each bit error, monitoring memory addresses presented to the data PROM, if a memory address presented to the data memory portion is an identified memory address, reading from the error PROM the bit position of each bit error and the correct bit data for each bit error, and substituting the correct bit data into each identified bit position of a sense amplifier reading data from the data memory portion.