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公开(公告)号：US20250102550A1
公开(公告)日：2025-03-27
申请号：US18825273
申请日：2024-09-05
Inventor： SHOGO KAWAHARA , YOSHIKAZU FURUTA , TOMOHIRO NEZUKA
IPC: G01R27/08 , G01R31/374 , G01R31/3835 , G01R31/396
Abstract: A shunt resistance measurement circuit is adapted to a shunt-based current sensor configured to measure a resistance value of a shunt resistor. The shunt resistance measurement circuit includes a control circuit, a switching power supply circuit, a voltage measurement circuit, and a signal processing circuit. The control circuit outputs a control signal including an AC carrier signal. The switching power supply circuit is operated by the control signal to output a power supply to the shunt resistor. The voltage measurement circuit measures a voltage across the shunt resistor. The signal processing circuit measures the resistance value of the shunt resistor by executing signal processing, based on the voltage measured by the voltage measurement circuit.
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公开(公告)号：US20250102421A1
公开(公告)日：2025-03-27
申请号：US18777707
申请日：2024-07-19
Inventor： MITSUYASU ABE
IPC: G01N19/02 , B60W40/068
Abstract: A road surface friction estimation device includes: a first estimation part to calculate a provisional maximum friction value based on a physical quantity in relation to friction between a road surface and a tire; a range determination part to determine a determination range of the provisional maximum friction value based on an average value and a standard deviation of the provisional maximum friction values; and a second estimation part to determine the provisional maximum friction value as an estimated maximum friction value when the provisional maximum friction value is within the determination range. The second estimation part determines a corrected value, which is a value within the determination range, as the estimated maximum friction value when the provisional maximum friction value is out of the determination range.
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公开(公告)号：US12255753B2
公开(公告)日：2025-03-18
申请号：US18187123
申请日：2023-03-21
Inventor： Yoshikazu Furuta , Shigeki Otsuka , Takasuke Ito , Hyoungjun Na , Tomohiro Nezuka
IPC: H04L12/40 , G01R31/396
Abstract: An insulated communication system includes a communication controller that sets communication data to a communication symbol through a numeral system and executes insulated communication through an insulator by adopting the communication symbol. The numeral system includes multiple states having a positive state, a negative state and a zero state. The positive state is represented by at least one positive integer, and the negative state is represented by at least one negative integer. The zero state is represented by zero being a level without generating current consumption. An absolute value of the at least one positive integer and an absolute value of the at least one negative integer are identical to each other. The communication controller sets an initial section of the communication data in the communication symbol to the positive state or the negative state, and sets a following section of the communication data to one of the multiple states.
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公开(公告)号：US12255243B2
公开(公告)日：2025-03-18
申请号：US17716213
申请日：2022-04-08
Inventor： Eiji Kagoshima , Yohei Iwahashi
IPC: H01L29/423 , H01L29/10 , H01L29/66 , H01L29/78
Abstract: A method for manufacturing a switching device includes: forming a trench at a top surface of a semiconductor substrate; forming a gate insulation film for covering an inner surface of the trench; forming a gate electrode inside the trench to locate a top surface of the gate electrode below the top surface of the semiconductor substrate; forming an oxide film by oxidizing the top surface of the gate electrode; forming an interlayer insulation film by vapor phase growth at a top surface of the oxide film to locate a top surface of the interlayer insulation film below the top surface of the semiconductor substrate; and forming an upper electrode in contact with the semiconductor substrate at the top surface of the semiconductor substrate and a side surface of the trench located above the top surface of the interlayer insulation film.
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公开(公告)号：US12255120B2
公开(公告)日：2025-03-18
申请号：US17824004
申请日：2022-05-25
Inventor： Yoshitaka Kato , Takeshi Endo , Kazuhiro Tsuruta
IPC: H01L21/56 , H01L23/31 , H01L23/433
Abstract: A semiconductor device includes a power module, a circuit package, and a joint portion joining the power module and the circuit package. The circuit package includes a semiconductor element, a wiring layer electrically connected with the semiconductor element, a heat conductive member, and a second mold resin portion sealing the semiconductor element and the heat conductive member. The wiring layer includes a connecting portion connected with the heat conductive member. One of the connecting portion or the heat conductive member is joined with a signal wire in the power module via the joint portion. The heat conductive member penetrates the second mold resin portion in a thickness direction of the semiconductor element. The heat conductive member and the connecting portion are arranged in a straight line in the thickness direction of the semiconductor element.
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Patent Agency Ranking
公开(公告)号：US20250081626A1
公开(公告)日：2025-03-06
申请号：US18753221
申请日：2024-06-25
Inventor： MASATO NOBORIO , JUN SAITO
IPC: H01L27/02
Abstract: A semiconductor device includes a semiconductor substrate having at least one element region in which a transistor is disposed, an interlayer insulating film disposed above the semiconductor substrate, and a semiconductor layer disposed above the interlayer insulating film. The semiconductor layer includes a first semiconductor layer of a first conductivity type connected to a gate of the transistor, a second semiconductor layer of a second conductivity type connected to the first semiconductor layer, and a third semiconductor layer of the first conductivity type connected to the second semiconductor layer and connected to a low potential terminal of the transistor.
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公开(公告)号：US20250044508A1
公开(公告)日：2025-02-06
申请号：US18668813
申请日：2024-05-20
Inventor： Tatsuya KAMIYA , Yuki KAMATA , Toshihiro ODA
IPC: G02B6/122
Abstract: A phase adjuster includes: a first optical path extending along a predetermined direction to propagate a first light; and a second optical path extending along the predetermined direction to propagate a second light different from the first light. The first optical path and the second optical path oppose to each other. A portion of the first optical path and a portion of the second optical path are formed of members having different light refractive indexes.
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公开(公告)号：US20250023963A1
公开(公告)日：2025-01-16
申请号：US18734148
申请日：2024-06-05
Inventor： Tetsuro TAKIZAWA
Abstract: A data transmission system executes data transmission bidirectionally between two electronic devices. The data transmission system includes a first unidirectional transmission path, a second unidirectional transmission path, a bidirectional transmission path, and a transmission direction setting device. The first unidirectional transmission path allows data transmission in a first direction from one of the two electronic devices to another one of the two electronic devices. The second unidirectional transmission path allows data transmission between the two electronic devices in a second direction being opposite to the first direction. The bidirectional transmission path allows data transmission between the two electronic devices in a data transmission direction set to be either the first direction or the second direction. The transmission direction setting device sets the data transmission direction for the bidirectional transmission path.
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公开(公告)号：US12188151B2
公开(公告)日：2025-01-07
申请号：US18069366
申请日：2022-12-21
Inventor： Hiroaki Fujibayashi , Masatake Nagaya , Junji Ohara , Shinichi Hoshi , Takashi Kanemura
IPC: C30B29/36 , C30B25/20 , H01L21/683 , H01L21/78 , H01L29/16
Abstract: A silicon carbide wafer includes a base wafer that is made of silicon carbide and doped with an n-type impurity, and an epitaxial layer that is arranged on a main surface of the base wafer, made of silicon carbide and doped with an n-type impurity. The base wafer has a thickness t1 and an average impurity concentration n1, and the epitaxial layer has a thickness t2 and an average impurity concentration n2. The base wafer and the epitaxial layer are configured so as to satisfy a mathematical formula 1: −0.0178
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公开(公告)号：US20240428571A1
公开(公告)日：2024-12-26
申请号：US18663579
申请日：2024-05-14
Inventor： HYOUNGJUN NA , HIDEHO ARAKIDA , TETSURO TAKIZAWA , TATSUYA TOKUE
IPC: G06V10/776 , G06V10/764 , G06V10/82 , G06V10/94
Abstract: A computation system using a neural network model includes: processor cores; a computation allocation unit that determines a computation processor core; and an anomaly detection unit that detects an anomaly in the computation processor core. The computation allocation unit causes an anomaly detection processor core to execute an anomaly detection computation. When a difference between a first computation result of a basic computation and a second computation result of the anomaly detection computation satisfies an allowance condition, the anomaly detection unit determines that the computation processor core and the anomaly detection processor core are normal. When the difference does not satisfy the allowance condition, the anomaly detection unit determines that at least a part of the computation processor core and the anomaly detection processor core has anomaly.
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