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公开(公告)号：US20220130747A1
公开(公告)日：2022-04-28
申请号：US17511371
申请日：2021-10-26
Inventor： Jie WANG , Jian TIAN , Jie LEI , Xintao WU , Chunjian LIU , Qin ZENG , Zouming XU
IPC: H01L23/498 , H01L33/62
Abstract: A light-emitting substrate includes a base, a first conductive pattern layer disposed on the base and a second conductive pattern layer disposed on a side of the first conductive pattern layer away from the base. The first conductive pattern layer includes first signal lines. The second conductive pattern layer includes lamp bead pads. The lamp bead pads include first lamp bead pads and at least one second lamp bead pad. A vertical projection of each first lamp bead pad on the base at least partially overlaps with a vertical projection of a first signal line on the base. A vertical projection of each second lamp bead pad on the base is outside vertical projections of the first signal lines on the base. A distance between a first lamp bead pad and the base is substantially the same as a distance between a second lamp bead pad and the base.
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公开(公告)号：US11316427B2
公开(公告)日：2022-04-26
申请号：US16833855
申请日：2020-03-30
Inventor： Lixin Zhu , Chunyang Nie , Ke Dai , Lei Guo , Ruilian Li , Xueqin Wei
IPC: H02M3/156
Abstract: A voltage control circuit comprises a sampling sub-circuit and a control sub-circuit. The sampling sub-circuit is configured to detect a potential difference between an output voltage and an input voltage to obtain a first voltage and output the first voltage to the control sub-circuit. The control sub-circuit is configured to compare a magnitude of the first voltage with a first voltage threshold, if the first voltage is less than the first voltage threshold, output the input voltage as the output voltage, and, if the first voltage is greater than or equal to the first voltage threshold, superimpose and output the input voltage and a bootstrap voltage as the output voltage.
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公开(公告)号：US11315999B2
公开(公告)日：2022-04-26
申请号：US16335332
申请日：2018-07-06
Abstract: The disclosure provides an array substrate, a display panel, a display device, and a method for fabricating the same. The array substrate provided by the present disclosure includes a substrate, a wiring on the substrate, an insulating layer covering the wiring, and a protrusion on the insulating layer and located in a non-display region of the array substrate. Wherein the protrusion is adjacent to the wiring, and wherein a surface, away from the base substrate, of the protrusion is further away from the base substrate than a surface, away from the base substrate, of a portion of the first insulating layer covering the wiring.
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公开(公告)号：US20220113838A1
公开(公告)日：2022-04-14
申请号：US17422100
申请日：2020-08-14
Inventor： Jiawei XU , Zhao DONG , Wenjin FAN , Le LI , Bisheng LI
Abstract: A touch substrate includes a base, a first electrode layer, a dielectric layer and a second electrode layer that are sequentially stacked on the base. The first electrode layer has first electrode regions and first auxiliary regions, and the second electrode layer has second electrode regions and second auxiliary regions. The first electrode layer includes a first mesh electrode including first mesh sub-electrodes and second mesh sub-electrodes. A region where each first mesh sub-electrode is located overlaps a second electrode region, and a region where each second mesh sub-electrode is located overlaps a second auxiliary region. The second electrode layer includes a second mesh electrode including third mesh sub-electrodes and fourth mesh electrodes. A region where each third mesh sub-electrode is located overlaps a first electrode region, and a region where the fourth mesh sub-electrode is located overlaps a first auxiliary region.
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公开(公告)号：US11300821B2
公开(公告)日：2022-04-12
申请号：US16618239
申请日：2019-05-31
Inventor： Yan Chen , Guohua Wang , Xing Su
IPC: G02F1/1333 , G02F1/13 , G02F1/1339 , G02F1/1335
Abstract: The present disclosure relates to a method of preparing a display substrate. The method may include forming a pattern layer on a base substrate; forming a planarization layer on the pattern layer, the planarization layer comprising a host material and a hydrophilic material and a hydrophobic material mixed in the host material; treating the planarization layer so that the host material reacts with the hydrophilic material to form a hydrophilic polymer, the host material reacts with the hydrophobic material to form a hydrophobic polymer, and the planarization layer is delaminated to form a first sub-planarization layer and a second sub-planarization layer; and cleaning the planarization layer with a cleaning solution that reacts with the hydrophobic polymer to remove at least part of the first sub-planarization layer. The first sub-planarization layer includes the hydrophobic polymer, and the second sub-planarization layer includes the hydrophilic polymer.
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Patent Agency Ranking
公开(公告)号：US11295648B2
公开(公告)日：2022-04-05
申请号：US16760062
申请日：2019-12-06
Inventor： Guangying Mou , Jideng Zhou , Yifeng Zou , Fengzhen Lv
Abstract: The present disclose is related to a gate drive unit. The gate drive unit may include a shift register; and a signal filter. The signal filter may respectively connect to a clock signal terminal, a filter output terminal, an input terminal and a reset terminal. The signal filter may be configured, under control of an effective signal provided by the input terminal, to transmit a clock signal of the clock signal terminal to the filter output terminal after the input terminal stops providing the effective signal and before the reset terminal provides an effective signal and, under control of an effective signal provided by the reset terminal, to disconnect the clock signal terminal and the filter output terminal.
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公开(公告)号：US11287333B2
公开(公告)日：2022-03-29
申请号：US16614788
申请日：2019-05-17
Inventor： Qinghe Wang , Dongfang Wang , Bin Zhou , Ce Zhao , Tongshang Su , Leilei Cheng , Yang Zhang , Guangyao Li
Abstract: A pressure sensing unit includes: a first substrate and a second substrate opposite to each other; and at least one vertical thin film transistor disposed between the first substrate and the second substrate. Each vertical thin film transistor includes a first electrode, a semiconductor active layer, a second electrode, at least one insulating support, and a gate electrode sequentially disposed in a direction extending from the first substrate to the second substrate. A first air gap is formed by the presence of the at least one insulating support between the gate electrode and the second electrode of each vertical thin film transistor.
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公开(公告)号：US20220093723A1
公开(公告)日：2022-03-24
申请号：US17483504
申请日：2021-09-23
Inventor： Liangchen YAN , Jun GENG , Tongshang SU , Wei HE , Bin ZHOU
IPC: H01L27/32
Abstract: A display backplane, a manufacturing method thereof, and a display device are provided. The display backplane includes a base substrate. A thin film transistor array layer, a protective layer, a planarization layer, and a light-emitting element are arranged on the base substrate. A first through hole is formed in the protective layer, and a second through hole is formed in the planarization layer. The first through hole and the second through hole are connected. A source electrode or a drain electrode is electrically connected to an anode via the first through hole and the second through hole. Each of the first through hole and the second through hole has a sidewall inclined relative to the base substrate.
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公开(公告)号：US20220076645A1
公开(公告)日：2022-03-10
申请号：US17459975
申请日：2021-08-27
Inventor： Bingbing YAN , Ke DAI , Liugang ZHOU , Chunyang NIE
IPC: G09G3/36
Abstract: A pixel driving circuit, a pixel driving method, an array substrate and a display device are provided. The pixel driving circuit includes a plurality of pixel regions; a pixel electrode array; and a thin film transistor switch, where at least one thin film transistor switch is arranged in each pixel region; the polarities of input voltage signals to two adjacent pixel electrodes are opposite in a same row of pixel electrodes; M rows of pixel electrodes are divided into Q pixel groups, including a first pixel group, a second pixel group and (Q−2) third pixel groups located between the first pixel group and the second pixel group, and each third pixel group includes at least q rows of pixel electrodes; and in the same column of pixel electrodes, the polarities of input voltage signals to the pixel electrodes in the same pixel group are the same, and the polarities of input voltage signals to the pixel electrodes of two adjacent pixel groups are opposite.
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公开(公告)号：US11264588B2
公开(公告)日：2022-03-01
申请号：US16338299
申请日：2018-08-03
Inventor： Jiewei Li , Chuan Yin , Xianjiang Xiong , Zhongsheng Qi , Litao Qu
Abstract: There is provided a metal encapsulation structure and a production method thereof, an encapsulation method for a display panel, and a display device. This production method comprises steps of: providing a metal film having a first surface and a second surface opposite to the first surface; forming a silane film on the first surface of the metal film, wherein a surface of the silane film away from the metal film has an active group; and attaching the first surface formed with the silane film to an adhesive layer, so as to react and bond the active group and the adhesive layer.
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