公开(公告)号：US08722514B2

公开(公告)日：2014-05-13

申请号：US13007892

申请日：2011-01-17

Applicant: Carsten von Koblinski ,  Volker Strutz ,  Manfred Engelhardt

Inventor： Carsten von Koblinski ,  Volker Strutz ,  Manfred Engelhardt

IPC: H01L21/30 ,  H01L21/46 ,  H01L23/31

CPC classification number: H01L43/14 ,  H01L21/78 ,  H01L21/84 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/06 ,  H01L27/12 ,  H01L27/22 ,  H01L43/04 ,  H01L43/065 ,  H01L43/12 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment, a semiconductor device includes a glass substrate, a semiconductor substrate disposed on the glass substrate, and a magnetic sensor disposed within and/or over the semiconductor substrate.

Abstract translation: 在一个实施例中，半导体器件包括玻璃衬底，设置在玻璃衬底上的半导体衬底和设置在半导体衬底内和/或之上的磁传感器。

公开(公告)号：US20130307609A1

公开(公告)日：2013-11-21

申请号：US13472012

申请日：2012-05-15

Applicant: Udo Ausserlechner

Inventor： Udo Ausserlechner

IPC: H03K17/90 ,  H01L43/14 ,  H01L43/04

CPC classification number: H01L43/04 ,  G01R33/07 ,  H01L43/065 ,  H01L43/14 ,  H03K17/90

Abstract: Embodiments of the present invention provide a Hall effect device that includes a Hall effect region of a first semiconductive type, at least three contacts and a lateral conductive structure. The Hall effect region is formed in or on top of a substrate, wherein the substrate includes an isolation arrangement to isolate the Hall effect region in a lateral direction and in a depth direction from the substrate or other electronic devices in the substrate. The at least three contacts are arranged at a top of the Hall effect region to supply the Hall effect device with electric energy and to provide a Hall effect signal indicative of the magnetic field, wherein the Hall effect signal is generated in a portion of the Hall effect region defined by the at least three contacts. The lateral conductive structure is located between the Hall effect region and the isolation arrangement.

Abstract translation: 本发明的实施例提供一种霍尔效应器件，其包括第一半导体型霍尔效应区域，至少三个触点和横向导电结构。 霍尔效应区形成在衬底的顶部或顶部，其中衬底包括隔离装置，用于在衬底或衬底中的其它电子器件的横向和深度方向上隔离霍尔效应区域。 至少三个触点设置在霍尔效应区域的顶部，以向霍尔效应器件提供电能并提供表示磁场的霍尔效应信号，其中霍尔效应信号在霍尔的一部分中产生 效果区域由至少三个触点限定。 横向导电结构位于霍尔效应区域和隔离装置之间。

公开(公告)号：US08114684B2

公开(公告)日：2012-02-14

申请号：US12396288

申请日：2009-03-02

Applicant: Thomas Rocznik ,  Christoph Lang ,  Sam Kavusi

Inventor： Thomas Rocznik ,  Christoph Lang ,  Sam Kavusi

IPC: H01L29/82 ,  H01L21/8238

CPC classification number: H01L43/065 ,  G01R33/07 ,  G01R33/077 ,  H01L43/14

Abstract: A complementary metal oxide semiconductor (CMOS) sensor system in one embodiment includes a doped substrate, a doped central island extending downwardly within the doped substrate from an upper surface of the doped substrate, and a first doped outer island extending downwardly within the doped substrate from the upper surface of the doped substrate, the first outer island electrically isolated from the central island within an upper portion of the substrate, and electrically coupled to the central island within a lower portion of the substrate.

Abstract translation: 在一个实施例中，互补金属氧化物半导体（CMOS）传感器系统包括掺杂衬底，在掺杂衬底内从掺杂衬底的上表面向下延伸的掺杂中心岛，以及在掺杂衬底内向下延伸的第一掺杂外部岛， 掺杂衬底的上表面，第一外岛与衬底的上部内的中心岛电隔离，并且电耦合到衬底的下部内的中心岛。

公开(公告)号：US20110204887A1

公开(公告)日：2011-08-25

申请号：US12711471

申请日：2010-02-24

Applicant: Udo Ausserlechner ,  Mario Motz

Inventor： Udo Ausserlechner ,  Mario Motz

IPC: G01R33/06 ,  G01R17/10

CPC classification number: H01L43/04 ,  G01R1/00 ,  G01R15/202 ,  G01R15/207 ,  H01L21/00 ,  H01L24/48 ,  H01L24/49 ,  H01L43/14 ,  H01L2221/00 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a conductor portion having a first portion and a second portion; at least three slots formed in the conductor portion between the first and second portions, each of the at least three slots having a length and at least one tip portion; at least two bridge portions each having a width separating two of the at least three slots and a length coupling the first and second portions; a first contact region disposed relative to the first portion and a second contact region disposed relative to the second portion; and at least one pair of magnetic sensor elements, a first pair of magnetic sensor elements arranged relative to and spaced apart from a first of the at least two bridge portions.

Abstract translation: 实施例涉及电流传感器和方法。 在一个实施例中，电流传感器包括具有第一部分和第二部分的导体部分; 在所述第一和第二部分之间的所述导体部分中形成有至少三个槽，所述至少三个槽中的每一个具有长度和至少一个末端部分; 至少两个桥接部分，每个桥部分具有分开所述至少三个狭槽中的两个的宽度以及耦合所述第一和第二部分的长度; 相对于第一部分设置的第一接触区域和相对于第二部分设置的第二接触区域; 以及至少一对磁性传感器元件，第一对磁性传感器元件相对于所述至少两个桥接部分中的第一个布置并相对于所述至少两个桥接部分中的第一个布置。

公开(公告)号：US20110147865A1

公开(公告)日：2011-06-23

申请号：US12642338

申请日：2009-12-18

Applicant: David Erie ,  Noel Hoilien ,  Steven Kosier

Inventor： David Erie ,  Noel Hoilien ,  Steven Kosier

IPC: H01L43/06 ,  H01L43/14

CPC classification number: H01L43/065 ,  H01L43/14

Abstract: A Hall effect transducer in a semiconductor wafer comprises a first layer of semiconducting material, a second layer of semiconducting material, and a contact structure configured to provide a path for electrical current to pass through the second layer. The second layer has higher electron hole mobility than the first layer, and is epitaxially grown atop the first layer.

Abstract translation: 半导体晶片中的霍尔效应传感器包括第一层半导体材料，第二层半导体材料和接触结构，其被配置为提供用于电流通过第二层的路径。 第二层比第一层具有更高的电子空穴迁移率，并且在第一层顶部外延生长。

公开(公告)号：US20090001351A1

公开(公告)日：2009-01-01

申请号：US12087149

申请日：2006-12-27

Applicant: Ichiro Shibasaki ,  Hirotaka Geka ,  Atsushi Okamoto

Inventor： Ichiro Shibasaki ,  Hirotaka Geka ,  Atsushi Okamoto

IPC: H01L27/22 ,  H01L21/20

CPC classification number: G01R33/06 ,  H01L43/065 ,  H01L43/08 ,  H01L43/12 ,  H01L43/14

Abstract: The present invention relates to a thin film lamination to be used in a micro InSb thin film magnetic sensor which can directly detect a magnetic flux density with high sensitivity and has small power consumption and consumption current, and the InSb thin film magnetic sensor. The InSb thin film magnetic sensor uses an InSb thin film as a magnetic sensor section or a magnetic detecting section. The sensor includes an InSb layer that is an InSb thin film formed on a substrate, and an AlxGayIn1-x-ySb mixed crystal layer (0≦x, y≦1) which shows resistance higher than the InSb layer or insulation, or p-type conduction, and has a band gap larger than that of InSb. The mixed crystal layer is provided between the substrate and the InSb layer, and has a content of Al and Ga atoms (x+y) in the range of 5.0 to 17%.

Abstract translation: 本发明涉及一种用于微型InSb薄膜磁传感器中的薄膜层压体，其可以高灵敏度地直接检测磁通密度并且具有小的功耗和消耗电流，以及InSb薄膜磁传感器。 InSb薄膜磁传感器使用InSb薄膜作为磁传感器部分或磁检测部分。 传感器包括作为形成在基板上的InSb薄膜的InSb层和表现出高于InSb层或绝缘体的电阻的Al x Ga y In 1-x-y Sb混合晶体层（0 <= x，y <= 1），或 p型导电，并且具有比InSb大的带隙。 混合晶体层设置在基板和InSb层之间，Al和Ga原子的含量（x + y）在5.0〜17％的范围内。

公开(公告)号：US20080135959A1

公开(公告)日：2008-06-12

申请号：US11608507

申请日：2006-12-08

Applicant: Horst Theuss ,  Albert Auburger

Inventor： Horst Theuss ,  Albert Auburger

IPC: H01L43/06 ,  H01L43/14 ,  H01L43/00

CPC classification number: H01L27/22 ,  G01R33/0005 ,  G01R33/072 ,  G01R33/091 ,  H01L43/04 ,  H01L43/14

Abstract: The invention relates to a semiconductor component (100) comprising a semiconductor chip (10) configured as a wafer level package, a magnetic field sensor (11) being integrated into said semiconductor chip.

Abstract translation: 本发明涉及一种包括半导体芯片（10）的半导体元件（100），其被配置为晶片级封装，一个集成在所述半导体芯片中的磁场传感器（11）。

公开(公告)号：US20070267709A1

公开(公告)日：2007-11-22

申请号：US11819544

申请日：2007-06-28

Applicant: Satoshi Oohira

Inventor： Satoshi Oohira

IPC: H01L43/04

CPC classification number: G01R33/077 ,  G01R33/066 ,  G01R33/07 ,  H01L43/065 ,  H01L43/14

Abstract: A vertical Hall device includes: a substrate; a semiconductor region having a first conductive type and disposed in the substrate; and a magnetic field detection portion disposed in the semiconductor region. The magnetic field detection portion is capable of detecting a magnetic field parallel to a surface of the substrate in a case where a current flows through the magnetic field detection portion in a vertical direction of the substrate. The semiconductor region is a diffusion layer including a conductive impurity doped and diffused therein. The semiconductor region is made of diffusion layer so that the device has high design degree of freedom.

Abstract translation: 垂直霍尔装置包括：基板; 具有第一导电类型并设置在所述衬底中的半导体区域; 以及设置在半导体区域中的磁场检测部。 在电流沿基板的垂直方向流过磁场检测部的情况下，磁场检测部能够检测与基板的表面平行的磁场。 半导体区域是包含掺杂并扩散在其中的导电杂质的扩散层。 半导体区域由扩散层制成，使得器件具有高设计自由度。

公开(公告)号：US20050174112A1

公开(公告)日：2005-08-11

申请号：US11050672

申请日：2005-02-07

Applicant: Shinji Wakabayashi ,  Satoshi Oohira ,  Takashi Kawashima

Inventor： Shinji Wakabayashi ,  Satoshi Oohira ,  Takashi Kawashima

IPC: G01B7/14 ,  G01D5/14 ,  G01R33/07 ,  H01L43/04 ,  H01L43/06 ,  H01L43/12 ,  H01L43/14

CPC classification number: G01R33/07 ,  G01D5/145 ,  H01L43/14

Abstract: Two Hall element forming arrangements are formed on a semiconductor substrate. Each Hall element forming arrangement includes a Hall element that is formed in a principal surface of the semiconductor substrate. A base is formed separately from the semiconductor substrate. Then, the base is disposed at a rear surface of the semiconductor substrate and holds the semiconductor substrate and the Hall element forming arrangements. The base includes a holding surface, which holds the semiconductor substrate, and two slant surfaces, each of which is slanted relative to the holding surface. Each Hall element forming arrangement is held on a corresponding one of the at least one slant surface of the base.

Abstract translation: 在半导体衬底上形成两个霍尔元件形成装置。 每个霍尔元件形成装置包括形成在半导体衬底的主表面中的霍尔元件。 基底与半导体衬底分开形成。 然后，将基底设置在半导体衬底的后表面并保持半导体衬底和霍尔元件形成装置。 基座包括保持半导体基板的保持表面和两个相对于保持表面倾斜的倾斜表面。 每个霍尔元件形成布置被保持在基座的至少一个倾斜表面中相应的一个上。

公开(公告)号：US20020016048A1

公开(公告)日：2002-02-07

申请号：US09886775

申请日：2001-06-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masaya Ueda ,  Tomoharu Sato ,  Masanaga Nishikawa

IPC: H01L021/20

CPC classification number: H01L43/12 ,  H01L21/02381 ,  H01L21/02466 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02549 ,  H01L21/02631 ,  H01L21/02658 ,  H01L43/14

Abstract: A method for manufacturing a semiconductor thin film having high carrier mobility, and a magnetoelectric conversion element provided with the semiconductor thin film manufactured by the aforementioned method are provided. The temperature of the Si single crystal substrate is raised to 270null C. to 320null C., and an In buffer layer is formed by an electron beam heating type vacuum evaporation method. Subsequently, an initial seed layer made of Sb and In is formed. The temperature of the Si single crystal substrate is raised to 460null C. to 480null C., and thereafter, a retention time approximated by a predetermined function of the temperature of the Si single crystal substrate is provided. Then, a main growth layer made of Sb and In is formed.

Abstract translation: 提供一种制造具有高载流子迁移率的半导体薄膜的方法，以及设置有通过上述方法制造的半导体薄膜的磁电转换元件。 将Si单晶衬底的温度升高到270℃至320℃，并通过电子束加热型真空蒸发法形成In缓冲层。 随后，形成由Sb和In制成的初始种子层。 将Si单晶衬底的温度升高到460℃至480℃，然后提供由Si单晶衬底的温度的预定函数近似的保留时间。 然后，形成由Sb和In构成的主生长层。