Computing system with error handling mechanism and method of operation thereof

    公开(公告)号:US10108483B2

    公开(公告)日:2018-10-23

    申请号:US14465694

    申请日:2014-08-21

    Abstract: A computing system includes: an inter-device interface configured to access a destination signal including an information portion for representing a content and an error-handling portion for describing the information portion relative to the content; a communication unit, coupled to the inter-device interface, configured to: generate a parity-check parameter based on a sparse configuration from the destination signal, and estimate the content based on decoding the information portion using the error-handling portion and the parity-check parameter.

    SYSTEM AND METHOD FOR DEEP LEARNING IMAGE SUPER RESOLUTION

    公开(公告)号:US20180293707A1

    公开(公告)日:2018-10-11

    申请号:US15671036

    申请日:2017-08-07

    Abstract: In a method for super resolution imaging, the method includes: receiving, by a processor, a low resolution image; generating, by the processor, an intermediate high resolution image having an improved resolution compared to the low resolution image; generating, by the processor, a final high resolution image based on the intermediate high resolution image and the low resolution image; and transmitting, by the processor, the final high resolution image to a display device for display thereby.

    Efficient polyphase architecture for interpolator and decimator

    公开(公告)号:US09966977B1

    公开(公告)日:2018-05-08

    申请号:US15402651

    申请日:2017-01-10

    CPC classification number: H04B1/0042 H04B1/0046 H04B3/462

    Abstract: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

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