公开(公告)号：US06191657B1

公开(公告)日：2001-02-20

申请号：US07731405

申请日：1991-07-02

申请人： Elie Brunet ,  Jean-Luc de Gouy ,  Thierry Ginestet

发明人： Elie Brunet ,  Jean-Luc de Gouy ,  Thierry Ginestet

IPC分类号： H03L700

CPC分类号： H03K23/68 ,  H03K23/667 ,  H03L7/1976 ,  H03L2207/10

摘要： A frequency synthesizer comprises a single phase-locked loop controlled by a reference clock formed by a voltage-controlled oscillator, a programmable divider with variable division rank M, a phase detector, and a loop filter. It also comprises a predetermined number n of fractional division structures, each implementing a frequency step Pi×FreF lower than the reference frequency Fref. Each fractional structure is coupled in parallel with said programmable divider to add to said division rank M fractional increments Pi such that the ratio between the frequency Fvco provided by said oscillator and said reference frequency be defined as a function of said increments Pi by the relationship: F vco = ( M ⁢ ∑ 1 n ⁢ P i ) ⁢ F ref .

摘要翻译： 频率合成器包括由电压控制振荡器形成的参考时钟控制的单个锁相环，具有可变分频等级M的可编程分频器，相位检测器和环路滤波器。 它还包括预定数量n的分数分割结构，每个分数结构实现比参考频率Fref低的频率步长PixFreF。 每个分数结构与所述可编程分频器并联耦合以添加到所述分割级M分数增量Pi，使得由所述振荡器提供的频率Fvco与所述参考频率之间的比率被定义为所述增量Pi的函数关系：

公开(公告)号：US06836188B2

公开(公告)日：2004-12-28

申请号：US10429188

申请日：2003-05-02

申请人： Jorg Bonhaus ,  Thomas Duda

发明人： Jorg Bonhaus ,  Thomas Duda

IPC分类号： H03L700

CPC分类号： H03L7/093 ,  H03L2207/50 ,  H04L7/0331

摘要： PLL circuit for eliminating self-jitter in a signal which is received by a control circuit, having a phase comparison circuit for producing a phase difference signal, which indicates the phase difference between the received signal and a fed-back output signal from the PLL circuit; having a loop filter for filtering the phase difference signal which is produced; having an oscillator, which is controlled by the filtered phase difference signal, for producing the output signal from the PLL circuit; with the loop filter having a nonlinear transfer function.

摘要翻译： PLL电路，用于消除由控制电路接收的信号中的自抖动，具有用于产生相位差信号的相位比较电路，其指示接收信号和来自PLL电路的反馈输出信号之间的相位差 ; 具有用于对产生的相位差信号进行滤波的环路滤波器; 具有由滤波相位差信号控制的用于产生来自PLL电路的输出信号的振荡器; 环路滤波器具有非线性传递函数。

公开(公告)号：US06836167B2

公开(公告)日：2004-12-28

申请号：US10198579

申请日：2002-07-17

申请人： Kathy L. Peng

发明人： Kathy L. Peng

IPC分类号： H03L700

CPC分类号： H03L7/0891 ,  H03L7/089

摘要： A phase locked loop that may use UP and/or DN signals having programmable active state durations to control the speed of a clock signal.

摘要翻译： 锁相环可以使用具有可编程有源状态持续时间的UP和/或DN信号来控制时钟信号的速度。

公开(公告)号：US06831523B1

公开(公告)日：2004-12-14

申请号：US10131002

申请日：2002-04-24

申请人： Douglas F. Pastorello ,  Michael H. Perrott

发明人： Douglas F. Pastorello ,  Michael H. Perrott

IPC分类号： H03L700

CPC分类号： H04L7/033 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/095 ,  H04L7/0004

摘要： An internal frequency reference, such as a VCO used in a PLL, having a free-running frequency fairly well controlled within a predictable range, is used to determine which of two possible modes of operation, a referenceless or reference clock mode of operation, is used based on a detected frequency of an externally-provided frequency reference signal. The frequency is detected without any additional externally provided signal to indicate the mode of operation or the frequency of the reference clock. If the frequency detection circuit detects a frequency below a predetermined threshold, referenceless mode of operation is indicated. Otherwise, reference clock mode of operation is indicated. In referenceless mode of operation such operations as frequency acquisition and lock detect are performed without the use of a reference clock. In reference clock mode the reference clock is used for such operations as frequency acquisition and lock detect.

摘要翻译： 使用在PLL中使用的具有在可预测范围内相当好地控制的自由运行频率的内部频率参考，例如VCO中使用的VCO，以确定两个可操作模式中的哪一种，无参考时钟或参考时钟操作模式 基于外部提供的频率参考信号的检测频率使用。 在没有任何附加的外部提供信号的情况下检测频率，以指示操作模式或参考时钟的频率。 如果频率检测电路检测到低于预定阈值的频率，则指示无操作的操作模式。 否则，将指示参考时钟工作模式。 在不使用参考时钟的情况下，执行诸如频率采集和锁定检测之类的操作的参考操作模式。 在参考时钟模式下，参考时钟用于频率采集和锁定检测等操作。

公开(公告)号：US06822493B2

公开(公告)日：2004-11-23

申请号：US10370395

申请日：2003-02-20

申请人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC分类号： H03L700

CPC分类号： H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

摘要： The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

公开(公告)号：US06819151B2

公开(公告)日：2004-11-16

申请号：US10651602

申请日：2003-08-29

申请人： Vladimir Mikhalev ,  Aaron M. Schoenfeld ,  Daniel B. Penney ,  William C. Waldrop

发明人： Vladimir Mikhalev ,  Aaron M. Schoenfeld ,  Daniel B. Penney ,  William C. Waldrop

IPC分类号： H03L700

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066 ,  H03L7/0812

摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.

公开(公告)号：US06809564B2

公开(公告)日：2004-10-26

申请号：US10197061

申请日：2002-07-17

申请人： John P. Hill

发明人： John P. Hill

IPC分类号： H03L700

CPC分类号： G06F1/04

摘要： The present invention includes an integrated circuit that can use a high-frequency timing reference generator from a high-speed serial interface to provide the clocking and timing requirements for the integrated circuit. The timing mechanism in the present invention obviates the need for phase locked loop (PLL) macrocells to provide timing reference and timing signals in the IC. The ICs of the present invention are preferably used as disk drive integrated circuits that include DSP, memory, data path controllers, data interfaces, custom macrocells, and DSP peripherals. The high-speed serial interface is preferably a Serial ATA (SATA), Universal Serial Bus (USB), Fiber Channel, or Serial Attached SCSI (SAS), among others. The present invention also includes a method of generating a timing reference signal in a IC that includes generating a high-frequency signal with the high-speed timing reference generator of a high-speed serial interface, then using a initial divider to generate a mid-frequency timing reference signal from the high-frequency timing reference signal, and then using a final divider to generate a final timing reference signal from the mid-frequency timing reference signal. In the present method, timing reference signals generated from a phase locked loop (PLL) macrocell are not required.

摘要翻译： 本发明包括可以使用来自高速串行接口的高频定时基准发生器来为集成电路提供时钟和定时要求的集成电路。 本发明的定时机制避免了锁相环（PLL）宏小区在IC中提供定时参考和定时信号的需要。 本发明的IC优选地用作包括DSP，存储器，数据路径控制器，数据接口，定制宏单元和DSP外围设备的磁盘驱动器集成电路。 高速串行接口优选地是串行ATA（SATA），通用串行总线（USB），光纤通道或串行连接SCSI（SAS）等。 本发明还包括一种在IC中产生定时参考信号的方法，该方法包括利用高速串行接口的高速定时基准发生器产生高频信号，然后使用初始分频器产生中频信号， 来自高频定时参考信号的高频定时参考信号，然后使用最终分频器从中频定时参考信号产生最终定时参考信号。 在本方法中，不需要从锁相环（PLL）宏单元产生的定时参考信号。

公开(公告)号：US06806751B2

公开(公告)日：2004-10-19

申请号：US10243193

申请日：2002-09-12

申请人： Charles Allen Helfinstine

发明人： Charles Allen Helfinstine

IPC分类号： H03L700

CPC分类号： H03L7/10 ,  H03L7/093 ,  Y10S331/02

摘要： A phase-locked loop having a phase detector for receiving a feedback signal and an input clock signal having an input clock frequency. The phase detector outputs or produces a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The phase-locked loop also has a loop filter coupled to the phase detector to receive the phase error signal and to output an error correction signal which includes an error correction frequency having a value ranging from about [input clock frequency−(input clock frequency×about 0.00015)] to about [input clock frequency+(input clock frequency×about 0.00015)]. A voltage controlled oscillator is coupled to the loop filter for receiving the error correction signal and to generate an output signal of the phase-locked loop which is indicative of the feedback signal. A method for operating a phase-locked loop circuit is provided along with a filter circuitry for a phase-locked loop and a method for filtering a phase error signal.

摘要翻译： 一种具有用于接收反馈信号的相位检测器和具有输入时钟频率的输入时钟信号的锁相环。 相位检测器输出或产生指示输入时钟信号和反馈信号之间的比较的相位误差信号。 锁相环还具有耦合到相位检测器的环路滤波器以接收相位误差信号并输出​​纠错信号，该纠错信号包括误差校正频率，该纠错频率的值范围从大约[输入时钟频率 - 输入时钟频率×0.00015 ）]〜[输入时钟频率+（输入时钟频率×0.00015）]。 压控振荡器耦合到环路滤波器，用于接收纠错信号并产生指示反馈信号的锁相环的输出信号。 提供了一种用于操作锁相环电路的方法以及用于锁相环的滤波器电路和用于滤波相位误差信号的方法。

公开(公告)号：US06801092B1

公开(公告)日：2004-10-05

申请号：US10409213

申请日：2003-04-08

申请人： Shervin Moloudi

发明人： Shervin Moloudi

IPC分类号： H03L700

CPC分类号： H03C3/0975 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L2207/06

摘要： A phase locked loop includes a difference detector, a loop filter, a controlled oscillation module, and a frequency translation module. The difference detector is operably coupled to determine a difference signal based on phase and/or frequency differences between a feedback oscillation and a reference oscillation. The loop filter is operably coupled to generate a control signal from the difference signal. The controlled oscillation module is operably coupled to produce, in accordance with an adjustable operating parameter, an output oscillation based on the controlled signal. The adjustable operating parameter is set based on desired operating conditions of the phase locked loop such that false locking of the phase locked loop is substantially avoided. The frequency translation module is operably coupled to produce the feedback oscillation from the output oscillation based on a frequency translation rate.

摘要翻译： 锁相环包括差分检测器，环路滤波器，受控振荡模块和频率转换模块。 差分检测器可操作地耦合以基于反馈振荡和参考振荡之间的相位和/或频率差来确定差分信号。 环路滤波器可操作地耦合以从差分信号产生控制信号。 受控振荡模块可操作地耦合以根据可调节的操作参数产生基于受控信号的输出振荡。 基于锁相环的期望操作条件来设定可调操作参数，从而基本上避免了锁相环的假锁定。 频率转换模块可操作地耦合以基于频率转换速率从输出振荡产生反馈振荡。

公开(公告)号：US06798258B2

公开(公告)日：2004-09-28

申请号：US10423344

申请日：2003-04-25

申请人： Stephen Andrew Rieven

发明人： Stephen Andrew Rieven

IPC分类号： H03L700

CPC分类号： H03H11/26

摘要： A precision signal delay apparatus and method for introducing time delay to a signal. Precision delay is introduced by a pair of delay locked loops (DLLs) connected in series each with selected delay (i.e., a Vernier-type circuit). Nonuniformity in the precision delay is compensated with a delay compensation circuit. The apparatus and method may be used for phase shifting, data delay, precision pulse width modulation, and precision time windowing.

摘要翻译： 一种用于将时间延迟引入信号的精密信号延迟装置和方法。 通过一对以选定的延迟串联连接的延迟锁定环（DLL）引入精确延迟（即，游标型电路）。 精度延迟的不均匀性由延迟补偿电路补偿。 该装置和方法可用于相移，数据延迟，精确脉冲宽度调制和精确时间窗口化。