公开(公告)号：US20050051826A1

公开(公告)日：2005-03-10

申请号：US10655654

申请日：2003-09-05

Applicant: Guy Blalock ,  Lyle Breiner

Inventor： Guy Blalock ,  Lyle Breiner

IPC: H01L21/02 ,  H01L21/8242 ,  H01L29/76

CPC classification number: H01L27/10852 ,  H01L28/84 ,  Y10S438/964

Abstract: The invention encompasses a method of forming a rugged silicon-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at a first temperature. The temperature is increased to a second temperature at least 40° C. higher than the first temperature while flowing at least one hydrogen isotope into the chamber. After the temperature reaches the second temperature, the layer is seeded with seed crystals. The seeded layer is then annealed to form a rugged silicon-containing surface. The rugged silicon-containing surface can be incorporated into a capacitor construction. The capacitor construction can be incorporated into a DRAM cell, and the DRAM cell can be utilized in an electronic system.

Abstract translation: 本发明包括形成坚固的含硅表面的方法。 在第一温度下在反应室内提供包含非晶硅的层。 当将至少一个氢同位素流入室内时，将温度升高至高于第一温度至少40℃的第二温度。 温度达到第二个温度后，该层用晶种接种。 接种层然后退火以形成坚固的含硅表面。 坚固的含硅表面可以并入电容器结构中。 电容器结构可以并入到DRAM单元中，并且可以在电子系统中使用DRAM单元。

公开(公告)号：US06501179B2

公开(公告)日：2002-12-31

申请号：US09921861

申请日：2001-08-02

Applicant: Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

Inventor： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC: H01L23485

CPC classification number: H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.

Abstract translation: 本发明包括在导电元件之间形成绝缘材料的方法。 在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。 另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。 在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。 在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

公开(公告)号：US06277731B1

公开(公告)日：2001-08-21

申请号：US09584256

申请日：2000-05-31

Applicant: Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

Inventor： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

IPC: H01L214763

CPC classification number: H01L23/5283 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract translation: 形成连接的方法包括沉积下导体的步骤。 电介质层沉积在下导体上，电介质层具有与下导体相邻的下表面，并具有上表面。 形成在电介质层的上表面和下表面之间延伸的开口。 导电插塞沉积在开口内，插头具有接近电介质层的上表面的上表面。 上表面具有插头的上表面与电介质层相邻的边缘。 在插头的上表面的边缘附近形成凹部，凹部延伸到插塞和介电层两者中。 最后，在电介质层的上表面和插头的上表面上沉积上导体。 还公开了如此形成的连接。

公开(公告)号：US06228772B1

公开(公告)日：2001-05-08

申请号：US09503412

申请日：2000-02-14

Applicant: Bradley J. Howard ,  Mark E. Jost ,  Guy Blalock

Inventor： Bradley J. Howard ,  Mark E. Jost ,  Guy Blalock

IPC: H01L21461

CPC classification number: H01L21/7684 ,  H01L21/76819

Abstract: A method for removing a surface defect from a dielectric layer during the formation of a semiconductor device comprises the steps of forming a dielectric layer having a hole therein, the dielectric also having a surface defect resulting from a previous manufacturing step such as chemical mechanical polish, contact with another surface during production, or from a manufacturing defect. A blanket conductive layer is then formed within the hole, within the surface defect, and over the dielectric layer. The conductive layer is etched from the surface of the dielectric using an etch which removes the conductive layer at a substantially faster rate than it removes the dielectric. This etch is stopped when the level of conductive material in the plug is flush with the upper surface of the dielectric. Next, the conductive and dielectric layers are etched using a dry or plasma etch which removes the conductive and dielectric layers at about the same rate. This etch continues until the surface defect in the dielectric layer is removed, thereby forming a nonrecessed plug.

Abstract translation: 在形成半导体器件期间从电介质层去除表面缺陷的方法包括以下步骤：在其中形成具有孔的电介质层，所述电介质还具有由以前的制造步骤产生的表面缺陷，例如化学机械抛光， 在生产过程中或与制造缺陷相接触。 然后在孔内，表面缺陷内，以及介电层上方形成覆盖层的导电层。 使用蚀刻以比其去除电介质更快的速率去除导电层的蚀刻从电介质的表面蚀刻导电层。 当塞子中的导电材料的水平与电介质的上表面齐平时，停止该蚀刻。 接下来，使用干燥或等离子体蚀刻蚀刻导电和介电层，其以大约相同的速率去除导电和介电层。 该蚀刻继续，直到电介质层中的表面缺陷被去除，从而形成未加工的插塞。

公开(公告)号：US6043151A

公开(公告)日：2000-03-28

申请号：US59759

申请日：1998-04-14

Applicant: Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

Inventor： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

IPC: H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/44

CPC classification number: H01L23/5283 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

公开(公告)号：US5994220A

公开(公告)日：1999-11-30

申请号：US595834

申请日：1996-02-02

Applicant: Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

Inventor： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

IPC: H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/44

CPC classification number: H01L23/5283 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

公开(公告)号：US5514246A

公开(公告)日：1996-05-07

申请号：US253115

申请日：1994-06-02

Applicant: Guy Blalock

Inventor： Guy Blalock

IPC: H01J37/32 ,  H05H1/00 ,  H05H1/46

CPC classification number: H01J37/32862 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/321 ,  H05H1/46 ,  Y10S438/905

Abstract: A plasma reactor includes, a) an electrically insulative shell forming a reactor cavity, the reactor cavity having internal walls; b) inductive coils positioned externally of the cavity; and c) a capacitive coupling plate positioned externally of the cavity intermediate the cavity and inductive coils, a power source being operably connected with the capacitive coupling plate. A method of cleaning away material adhering to internal walls of a plasma reactor includes, a) injecting a cleaning gas into the reactor, the cleaning gas comprising a species which when ionized is reactive with material adhering to the internal plasma reactor walls; and b) generating a capacitive coupling effect between a pair of conductors, at least one of which is positioned externally of the plasma reactor, effective to both ionize the cleaning gas into the reactive ionized species and draw such ionized species in the direction of the external conductor to impact and clean away material adhering to the reactor internal walls. A combination dry etching and cleaning process is also disclosed.

公开(公告)号：US5238862A

公开(公告)日：1993-08-24

申请号：US854435

申请日：1992-03-18

Applicant: Guy Blalock ,  Phillip G. Wald

Inventor： Guy Blalock ,  Phillip G. Wald

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10808 ,  H01L28/84 ,  H01L28/91 ,  Y10S438/964

Abstract: A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls; and e) providing conformal layers of capacitor dielectric and capacitor cell material atop the etched conductive material and over its exposed striated sidewalls. The invention also includes a stacked capacitor construction having an electrically conductive storage node with upwardly rising external sidewalls. Such sidewalls have longitudinally extending striations to maximize surface area and corresponding capacitance in a resulting construction.

Abstract translation: 在半导体晶片上形成电容器的方法包括：a）在干式蚀刻反应器中，利用选择的反应性气体组分的气体流速，选择性地各向异性地将具有最小选定开口尺寸的电容器接触开口刻蚀成绝缘介电层;以及 惰性气体轰击组分，轰击组分的流速显着超过反应组分的流速，以有效地产生具有沟槽条纹侧壁的电容器接触开口，从而限定母电容器接触开口条纹; b）在条纹电容器接触开口内提供导电存储节点材料层; c）去除所述导电材料层的至少一部分以在所述绝缘电介质内限定具有条纹侧壁的隔离电容器存储节点; d）相对于导电材料选择性地蚀刻绝缘介电层，足以露出至少一部分外部凸纹状导电材料侧壁; 以及e）在蚀刻的导电材料的顶部和其暴露的条纹侧壁上提供电容器电介质和电容器电池材料的保形层。 本发明还包括具有具有向上升高的外侧壁的导电存储节点的堆叠电容器结构。 这样的侧壁具有纵向延伸的条纹，以在最终结构中最大化表面积和相应的电容。