公开(公告)号：US09105466B2

公开(公告)日：2015-08-11

申请号：US14084823

申请日：2013-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Lee-Chung Lu ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Mei-Hui Huang

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5077 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11885

Abstract: An integrated circuit includes a first standard cell over a substrate, a power rail, and a first connection plug. The first standard cell includes an active area, at least one gate electrode overlapping the active area of the first standard cell, and at least one metallic line structure overlapping the active area of the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. The power rail is substantially orthogonal to the at least one metallic line structure of the first standard cell. The power rail overlaps the at least one metallic line structure of the first standard cell, and the power rail has a flat edge extending through the first standard cell. The first connection plug is at a region where the power rail overlaps the at least one metallic line structure of the first standard cell.

Abstract translation: 集成电路包括基板上的第一标准单元，电源导轨和第一连接插头。 第一标准单元包括有源区，与第一标准单元的有效区重叠的至少一个栅极，以及与第一标准单元的有源区重叠的至少一个金属线结构。 至少一个金属线结构基本上平行于栅电极。 电源轨基本上与第一标准单元的至少一个金属线结构正交。 电源轨道与第一标准单元的至少一个金属线结构重叠，并且电源轨具有延伸穿过第一标准单元的平坦边缘。 第一连接插头位于电源轨道与第一标准单元的至少一个金属线结构重叠的区域。

公开(公告)号：US20150062761A1

公开(公告)日：2015-03-05

申请号：US14031826

申请日：2013-09-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hui Chen ,  Chia-Hung Chu ,  Kuo-Ji Chen ,  Ming-Hsiang Song ,  Lee-Chung Lu

IPC: H02H9/04 ,  H03K3/011

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H01L27/0285 ,  H03K3/013 ,  H03K5/003 ,  H03K19/003 ,  H03K19/017509

Abstract: A circuit, a multiple power domain circuit, and a method are disclosed. An embodiment is a circuit including an input circuit having a first output and a second output, the input circuit being coupled to a first power supply voltage, and a level-shifting circuit having a first input coupled to the first output of the input circuit and a second input coupled to the second output of the input circuit, the level-shifting circuit being coupled to a second power supply voltage. The circuit further includes a first transistor coupled between a first node of the level-shifting circuit and the second power supply voltage, and a control circuit having an output coupled to a gate of the first transistor, the control circuit being coupled to the second power supply voltage.

Abstract translation: 公开了电路，多功率域电路和方法。 实施例是包括具有第一输出和第二输出的输入电路的电路，输入电路耦合到第一电源电压，以及电平移动电路，其具有耦合到输入电路的第一输出的第一输入，以及 耦合到所述输入电路的第二输出的第二输入，所述电平移动电路耦合到第二电源电压。 该电路还包括耦合在电平移动电路的第一节点和第二电源电压之间的第一晶体管和具有耦合到第一晶体管的栅极的输出的控制电路，该控制电路耦合到第二电源 电源电压。

公开(公告)号：US08898600B2

公开(公告)日：2014-11-25

申请号：US13941941

申请日：2013-07-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Yu-Hsiang Kao ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F7/0035 ,  G06F17/5072 ,  G06F2217/08 ,  G06F2217/12

Abstract: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.

Abstract translation: 布置目标图案的方法包括：将目标图案的第一特征的末端分配给保留区域，以及定位其他特征，使得目标图案的其它特征的末端在所述保留区域内没有结束 出区。 目标图案应形成相应的主要特征和切割图案。