公开(公告)号：US20150092314A1

公开(公告)日：2015-04-02

申请号：US14039192

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Mario Francisco Velez ,  Jonghae Kim ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Xiaonan Zhang ,  Ryan David Lane ,  Matthew Michael Nowak

IPC: H01F27/29 ,  H01F41/04 ,  H01F27/40

CPC classification number: H01F27/29 ,  H01F17/0006 ,  H01F27/40 ,  H01F2017/002 ,  H01F2017/0073 ,  Y10T29/4902

Abstract: A system includes a first connector coupled to a first surface of a substrate. The first connector enables the system to be electrically coupled to a first device external to the substrate. The system includes a second connector coupled to a second surface of the substrate. The system also includes a plurality of conductive vias extending through the substrate from the first surface to the second surface. The plurality of conductive vias surrounds the first connector and the second connector. The plurality of conductive vias is electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. A second lead of the toroidal inductor is electrically coupled to the second connector.

Abstract translation: 系统包括耦合到衬底的第一表面的第一连接器。 第一连接器使得系统能够电耦合到衬底外部的第一器件。 该系统包括耦合到基板的第二表面的第二连接器。 该系统还包括从第一表面延伸穿过基底的多个导电通孔到第二表面。 多个导电通孔围绕第一连接器和第二连接器。 多个导电通孔电耦合在一起以形成环形电感器。 环形电感器的第一引线电耦合到第一连接器。 环形电感器的第二引线电耦合到第二连接器。

公开(公告)号：US11616185B2

公开(公告)日：2023-03-28

申请号：US15611524

申请日：2017-06-01

Applicant: QUALCOMM Incorporated

Inventor： Jorge Luis Rosales ,  Victor Adrian Chiriac ,  Mario Francisco Velez ,  Peng Wang

IPC: H01L35/32 ,  H01L35/02 ,  H01L35/30 ,  H01L35/34

Abstract: A device that includes a region comprising a heat generating device, and an energy harvesting device coupled to the region comprising the heat generating device. The energy harvesting device includes a first thermal conductive layer, a thermoelectric generator (TEG) coupled to the first thermal conductive layer, and a second thermal conductive layer coupled the thermoelectric generator (TEG) such that the thermoelectric generator (TEG) is between the first thermal conductive layer and the second thermal conductive layer. In some implementations, the energy harvesting device includes an insulation layer.

公开(公告)号：US10944379B2

公开(公告)日：2021-03-09

申请号：US15379392

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Changhan Hobie Yun ,  Shiqun Gu ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim

IPC: H03H9/05 ,  H03H9/64 ,  H03H3/08 ,  H03H9/72 ,  H03H9/70 ,  H03H3/02

Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.

公开(公告)号：US10685924B2

公开(公告)日：2020-06-16

申请号：US15686131

申请日：2017-08-24

Applicant: QUALCOMM Incorporated

Inventor： Jon Bradley Lasiter ,  Ravindra Vaman Shenoy ,  Donald William Kidwell, Jr. ,  Mohammad Ali Tassoudji ,  Mario Francisco Velez

IPC: H01Q9/04 ,  H01L23/66 ,  H01L23/31 ,  H01L25/16 ,  H01L21/683 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01Q1/22 ,  H01Q21/28

Abstract: An package and related methods are disclosed. The package may include an antenna, an insert made of low-loss material, and a mold, wherein the mold directly contacts and surrounds at least a portion of the insert, wherein the antenna is formed of conductive material disposed at least in part on a surface of the insert.

公开(公告)号：US10607980B2

公开(公告)日：2020-03-31

申请号：US15861140

申请日：2018-01-03

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey Lan ,  Niranjan Sunil Mudakatte ,  Changhan Hobie Yun ,  Daeik Daniel Kim ,  Chengjie Zuo ,  David Francis Berdy ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01L27/01 ,  H01L23/15 ,  H01L23/522 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H01G2/02 ,  H01G4/005

Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.

公开(公告)号：US10354795B2

公开(公告)日：2019-07-16

申请号：US15242007

申请日：2016-08-19

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Xiangdong Zhang ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01F7/06 ,  H01F41/04 ,  H01F27/28 ,  H01F17/00

Abstract: A method includes forming a first conductive spiral and a second conductive spiral of a spiral inductor coupled to a substrate. The second conductive spiral overlays the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate. The second thickness is greater than the first thickness. The portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.

公开(公告)号：US10290414B2

公开(公告)日：2019-05-14

申请号：US14841132

申请日：2015-08-31

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Daeik Daniel Kim ,  David Francis Berdy ,  Je-Hsiung Jeffrey Lan ,  Jonghae Kim ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka

IPC: H01F5/00 ,  H01F27/28 ,  H01F27/245 ,  H01F41/14 ,  H01F41/04 ,  H01F17/00 ,  H01F41/32 ,  H01L23/64 ,  H05K1/16

Abstract: A substrate includes a first dielectric layer, a magnetic core at least partially in the first dielectric layer, where the magnetic core comprises a first non-horizontal thin film magnetic (TFM) layer. The substrate also includes a first inductor that includes a plurality of first interconnects, where the first inductor is positioned in the substrate to at least partially surround the magnetic core. The magnetic core may further include a second non-horizontal thin film magnetic (TFM) layer. The magnetic core may further include a core layer. The magnetic core may further include a third thin film magnetic (TFM) layer, and a fourth thin film magnetic (TFM) layer that is substantially parallel to the third thin film magnetic (TFM) layer.

公开(公告)号：US10249580B2

公开(公告)日：2019-04-02

申请号：US15190158

申请日：2016-06-22

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  David Francis Berdy ,  Chengjie Zuo ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01L23/64 ,  H01F41/04 ,  H01L23/522 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L27/08

Abstract: In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce integration density, decrease flexibility, increase footprint, and generally increase costs. To address such disadvantages, it is proposed to provide a part of an inductor in a substrate below a die. The proposed stacked substrate inductor may include a first inductor in a first substrate, a second inductor in a second a second substrate stacked on the first substrate, and an inductor interconnect coupling the first and second inductors. The core regions of the first and second inductors may overlap with each other at least partially. The proposed stacked substrate inductor may enhance integration density, increase flexibility, decrease footprint, and/or reduce costs.

公开(公告)号：US10242957B2

公开(公告)日：2019-03-26

申请号：US14633934

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  David Francis Berdy ,  Chengjie Zuo ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L23/60 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/552

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.

公开(公告)号：US10163771B2

公开(公告)日：2018-12-25

申请号：US15231512

申请日：2016-08-08

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Changhan Hobie Yun ,  David Francis Berdy ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Shiqun Gu ,  Jonghae Kim

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L25/00 ,  H01L27/092 ,  H01L49/02 ,  H01L23/48

Abstract: In a particular aspect, a device includes a substrate including at least one through-substrate via. A metal structure is disposed on a surface of the substrate. The device further includes a semiconductor layer bonded to the substrate. The semiconductor layer includes at least one complimentary metal-oxide-semiconductor (CMOS) transistor and a metal disposed within a second via. The metal is in direct contact with the metal structure.