公开(公告)号：USRE34463E

公开(公告)日：1993-11-30

申请号：US662663

申请日：1991-02-28

Applicant: Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

Inventor： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

IPC: G11C11/4076 ,  G11C11/4094 ,  G11C7/00 ,  G11C11/40

CPC classification number: G11C11/4094 ,  G11C11/4076

Abstract: A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

公开(公告)号：US5010259A

公开(公告)日：1991-04-23

申请号：US454580

申请日：1989-12-21

Applicant: Yoshinori Inoue ,  Masaki Kumanoya ,  Takahiro Komatsu ,  Yasuhiro Konishi ,  Katsumi Dosaka

Inventor： Yoshinori Inoue ,  Masaki Kumanoya ,  Takahiro Komatsu ,  Yasuhiro Konishi ,  Katsumi Dosaka

IPC: G11C11/407 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H02M3/07 ,  H03K5/02 ,  H03K19/017 ,  H03K19/094

CPC classification number: H03K19/01714

Abstract: An input signal is inverted by a CMOS inverter and provided for an output signal line. The CMOS inverter is provided between a power supply and a ground, and its node on the side of the power supply is charged all the time to prevent the potential thereof from being lowered. An output signal provided for the output signal line is delayed by a delay circuit to be applied to a boosting capacitor. The potential of the node is further boosted by this boosting capacitor. Consequently, the potential of the output signal is also boosted. When the potential of the node is raised higher than a supply voltage, an N channel MOSFET for charging is turned off to prevent a reverse flow of a charge.

Abstract translation: 输入信号由CMOS反相器反相并提供给输出信号线。 CMOS反相器设置在电源和地之间，并且其电源侧的节点一直被充电以防止其电位降低。 为输出信号线提供的输出信号被延迟电路延迟以施加到升压电容器。 该升压电容器进一步提升了节点的电位。 因此，输出信号的电位也得到提升。 当节点的电位升高到高于电​​源电压时，用于充电的N沟道MOSFET关闭，以防止电荷反向流动。

公开(公告)号：US4843596A

公开(公告)日：1989-06-27

申请号：US124554

申请日：1987-11-24

Applicant: Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

Inventor： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

IPC: G11C11/401 ,  G11C7/22 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C7/22

Abstract: A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.

Abstract translation: 一种新颖的半导体存储器件包括响应于地址变化的检测而产生短宽度脉冲的地址检测电路。 列解码器激活信号发生器检测短宽度脉冲的开始，并且响应于产生列解码器激活信号。 第二检测电路检测短宽度脉冲的结论，并产生触发前置放大器激活信号的第二脉冲，其激活前置放大器并锁存输入/输出线上存在的数据。 复位信号发生器产生复位信号以停用列解码器激活信号并延迟前置放大器激活信号。 当输出第一个脉冲时，前置放大器激活信号发生器和复位信号发生器被复位。

公开(公告)号：US4823322A

公开(公告)日：1989-04-18

申请号：US102683

申请日：1987-09-30

Applicant: Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

Inventor： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

IPC: G11C11/407 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/413 ,  G11C7/00

CPC classification number: G11C11/4076

Abstract: A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.

Abstract translation: 具有连接在一对输入/输出线之间的输入/输出负载和用于产生内部/ RAS信号的动态随机存取存储器件，该内部/ RAS信号具有相对于外部/ RAS信号的相同转变延迟的复位转变 。 内部/ RAS信号至少控制施加到所选择的存储单元的晶体管的字信号和施加到使能晶体管的使能信号，从而使存储器单元和使能晶体管变为不导通的时间被延迟 相对于连接在每对位线和输入/输出线之间的传输晶体管的时间变得不导通。

公开(公告)号：US4734890A

公开(公告)日：1988-03-29

申请号：US929369

申请日：1986-11-12

Applicant: Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

Inventor： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC: G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4099 ,  G11C11/40 ,  G11C13/00

CPC classification number: G11C11/4099 ,  G11C11/4087

Abstract: A dynamic RAM has dummy capacitors (C6, C7) having the same capacitance as a memory capacitor connected to a pair of bit lines (BL1, BL1), respectively. During an active period, respective dummy capacitors (C6, C7) are charged to the H level and L level, which are signal levels of the bit lines (BL1, BL1) and during precharge period, both dummy capacitors are equalized. Since both dummy capacitors (C6, C7) respectively connected to a pair of bit lines (BL1, BL1) are equalized during precharge period, so that the stored charge values of the dummy capacitors (C6, C7) both become the intermediate value of the ground level and supply potential level.

Abstract translation: 动态RAM分别具有与连接到一对位线（BL1，＆amp;上升和下降B1）的存储电容器相同的电容的虚拟电容器（C6，C7）。 在有效期间，将各个虚拟电容器（C6，C7）充电为位电平（BL1，上升和下降B1）的信号电平的H电平和L电平，并且在预充电期间，两个虚拟电容器被均衡。 由于分别连接到一对位线（BL1，＆lt;上升＆amp; B1）的两个虚拟电容器（C6，C7）在预充电期间均衡，所以虚拟电容器（C6，C7）的存储的电荷值均成为 地面水平和供应潜力水平。