公开(公告)号：US12245471B2

公开(公告)日：2025-03-04

申请号：US17788387

申请日：2021-08-04

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ying Han ,  Yicheng Lin ,  Ling Wang ,  Guoying Wang ,  Xing Zhang ,  Zhan Gao ,  Pan Xu

IPC: H01L27/14 ,  H01L27/12 ,  H10K50/86 ,  H10K59/121 ,  H10K59/13 ,  H10K59/131

Abstract: The display substrate includes: a substrate; a plurality of pixel units on the substrate, each pixel unit includes a plurality of sub-pixels, each sub-pixel includes a light-emitting element and a pixel drive circuit; a photosensitive circuit on the substrate; a first conductive film layer on the substrate. The pixel drive circuit includes a drive transistor, a gate electrode of the drive transistor is located on a side of a drive active layer away from the substrate, an orthographic projection of the gate electrode of the drive transistor on the substrate at least partially overlaps an orthographic projection of the drive active layer on the substrate. The first conductive film layer includes a first light-shielding portion between the substrate and the drive active layer, and an orthographic projection of the first light-shielding portion on the substrate at least partially overlaps the orthographic projection of the drive active layer on the substrate.

公开(公告)号：US12193290B2

公开(公告)日：2025-01-07

申请号：US17629772

申请日：2021-04-30

Applicant: Chengdu BOE Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Yuanjie Xu ,  Benlian Wang ,  Lili Du ,  Zhenhua Zhang ,  Yuxin Zhang ,  Pan Xu

IPC: H01L21/56 ,  G09G3/3233 ,  H10K59/12 ,  H10K59/121 ,  H10K59/131 ,  H10K59/35

Abstract: Provided are a display substrate, a preparation method thereof, and a display device. The display substrate includes a display region and a bonding region on one side of the display region. The bonding region at least includes a lead area; the display region includes a plurality of data lines and a plurality of data fanout lines, the lead area includes a plurality of lead wires, and orthographic projections of the plurality of data lines and the plurality of data fanout lines on a plane of the display substrate are at least partially overlapped. At least one lead wire is connected to the data line through the data fanout line. In the lead area, an orthographic projection of any one of the lead wires on the plane of the display substrate and orthographic projections of other lead wires on the plane of the display substrate have no overlap region.

公开(公告)号：US12082436B2

公开(公告)日：2024-09-03

申请号：US17279771

申请日：2020-06-02

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xing Zhang ,  Wei Quan ,  Yicheng Lin ,  Pan Xu ,  Ling Wang ,  Guoying Wang ,  Ying Han ,  Zhan Gao

IPC: H10K50/824 ,  H10K50/828 ,  H10K59/12 ,  H10K59/122 ,  H10K71/00

CPC classification number: H10K50/824 ,  H10K50/828 ,  H10K59/122 ,  H10K71/00 ,  H10K59/1201

Abstract: The present disclosure provides a display substrate, including: a base substrate, which includes a display region and a driving region arranged on at least one side of the display region; a first electrode layer disposed in the display region; a signal output part disposed in the driving region, the first electrode layer is electrically coupled to the signal output part, the first electrode layer comprises a plurality of electrode regions each having a same area; and a plurality of auxiliary electrodes, which are in one-to-one correspondence with the plurality of electrode regions and configured to be coupled in parallel with the first electrode layer, a resistance of each auxiliary electrode is inversely correlated with a minimum distance from the electrode region corresponding to said each auxiliary electrode to the signal output part. The present disclosure further provides a display panel and a manufacturing method thereof and a display device.

公开(公告)号：US12075664B2

公开(公告)日：2024-08-27

申请号：US16971673

申请日：2019-11-04

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guoying Wang ,  Yicheng Lin ,  Ling Wang ,  Zhen Song ,  Pan Xu ,  Xing Zhang ,  Ying Han ,  Zhan Gao

IPC: H10K59/13 ,  H10K59/12 ,  H10K59/121 ,  H10K59/124 ,  H10K59/126 ,  H10K59/131 ,  H10K59/38

CPC classification number: H10K59/13 ,  H10K59/1213 ,  H10K59/124 ,  H10K59/126 ,  H10K59/131 ,  H10K59/38 ,  H10K59/1201

Abstract: A display substrate having a plurality of subpixels is provided. A respective one of the plurality of subpixels includes a light emitting element; a first thin film transistor configured to driving light emission of the light emitting element; and a light emitting brightness value detector. The light emitting brightness value detector includes a second thin film transistor; and a photosensor electrically connected to the second thin film transistor and configured to detect a light emitting brightness value. The display substrate further includes a silicon organic glass layer on a side of at least one of the first thin film transistor or the second thin film transistor away from a base substrate; and the photosensor is on a side of the silicon organic glass layer away from the base substrate.

公开(公告)号：US20240155893A1

公开(公告)日：2024-05-09

申请号：US18261880

申请日：2022-09-06

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ying Han ,  Pan Xu ,  Xing Zhang ,  Chengyuan Luo ,  Donghui Zhao ,  Mingi Chu

IPC: H10K59/131 ,  G09G3/3233

CPC classification number: H10K59/131 ,  G09G3/3233 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/08 ,  G09G2320/0233

Abstract: A display substrate includes: a base substrate, a plurality of pixel units and a plurality of initialization voltage signal lines. The pixel units are arranged in an array to form a plurality of rows of pixel units and a plurality of columns of pixel units, at least one pixel unit includes sub-pixels, and at least one sub-pixel includes a light-emitting element and a pixel driving circuit. The initialization voltage signal lines are configured to provide initialization voltage signals to the plurality of rows of pixel units respectively, and are arranged at intervals along a second direction. At least one initialization voltage signal line extends along a first direction. The plurality of rows of pixel units include a (2n−1)th row and a 2nth row and pixel driving circuits of the (2n−1)th row and pixel driving circuits of the 2nth rows share a common initialization voltage signal line.

公开(公告)号：US20240038142A1

公开(公告)日：2024-02-01

申请号：US18042342

申请日：2022-05-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ying Han ,  Pan Xu ,  Xing Zhang ,  Chengyuan Luo ,  Donghui Zhao

IPC: G09G3/32 ,  H01L27/12

CPC classification number: G09G3/32 ,  H01L27/124 ,  G09G2300/0842 ,  G09G2310/0262 ,  G09G2300/0408 ,  G09G2320/02 ,  G09G2310/08 ,  H01L27/1222

Abstract: A display panel includes: a plurality of pixel circuits arranged on base substrate, at least one pixel circuit includes a drive transistor and a first switch transistor; an active layer arranged on base substrate and including a first active portion and a second active portion, the first active portion is configured to form a channel portion of the drive transistor, the second active portion is configured to form a second electrode connection portion of the first switch transistor; and a first conductive layer arranged on a side of the active layer away from the base substrate, the first conductive layer includes a first conductive portion, a portion of the first conductive portion is used to form a gate electrode of the drive transistor, another portion is electrically connected to the second active portion and a channel length of the channel portion of the drive transistor is greater than a channel width.

公开(公告)号：US11887527B2

公开(公告)日：2024-01-30

申请号：US17921585

申请日：2021-05-12

Applicant: BOE Technology Group Co., Ltd.

Inventor： Pan Xu ,  Yicheng Lin ,  Guoying Wang ,  Xing Zhang ,  Ying Han ,  Zhan Gao ,  Dacheng Zhang

IPC: G09G3/20 ,  G09F9/30

CPC classification number: G09G3/2092 ,  G09F9/30 ,  G09G3/20 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2310/0267 ,  G09G2320/0223

Abstract: A special-shaped display panel includes: a special-shaped display area (S) having gate lines (G), some of the gate lines (G) being cut off in a non-display sub-area (S2) of the special-shaped display area (S); a first gate drive circuit set (A1) located on one side of the special-shaped display area (S), electrically connected to one ends of gate lines (G) which are not cut off by the non-display sub-area (S2), and electrically connected to gate lines (G) on one side which are cut off by the non-display sub-area (S2); and a second gate drive circuit set (A2) located on the other side of the special-shaped display area (S), electrically connected to the other ends of gate lines (G) which are not cut off by the non-display sub-area (S2), and electrically connected gate lines (G) on the other side which are cut off by the non-display sub-area (S2).

公开(公告)号：US20240023399A1

公开(公告)日：2024-01-18

申请号：US18259460

申请日：2022-09-06

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ying Han ,  Pan Xu ,  Xing Zhang ,  Guoying Wang ,  Chengyuan Luo ,  Mingi Chu ,  Dacheng Zhang

IPC: H10K59/35 ,  H10K59/122 ,  H10K59/80

CPC classification number: H10K59/351 ,  H10K59/352 ,  H10K59/122 ,  H10K59/8792

Abstract: A display substrate, including a base substrate, a plurality of pixel units, and a pixel definition layer. The pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The fourth sub-pixel is a white sub-pixel, and any two of the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel display different colors. In at least one pixel unit, at least one of the first sub-pixel, the second sub-pixel and the third sub-pixel is located in a different row from the fourth sub-pixel. In at least one pixel unit, each of orthographic projections of a first opening of the first sub-pixel, a second opening of the second sub-pixel and a third opening of the third sub-pixel on the base substrate has an area less than that of a fourth opening of the fourth sub-pixel on the base substrate.

公开(公告)号：US11758780B2

公开(公告)日：2023-09-12

申请号：US17273290

申请日：2020-05-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Pan Xu ,  Yicheng Lin ,  Ling Wang ,  Guoying Wang ,  Xing Zhang ,  Ying Han

IPC: H01L27/32 ,  H10K59/131 ,  G09G3/3233 ,  G09G3/3266 ,  G11C19/28 ,  H01L25/18

CPC classification number: H10K59/131 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2300/0842 ,  G09G2310/0286 ,  G11C19/287 ,  H01L25/18

Abstract: Provided are a display substrate and display apparatus. The display substrate includes a display region and non-display region; base substrate, driving structure layer and wiring layer. The driving structure layer located in the display region includes a first power supply line, data signal line and reference signal line extending along a first direction; the wiring layer located in the non-display region includes a first power supply wiring electrically connected to first power supply line and located on first side of the display region, a data wiring located on second side, different from the first side, of the display region, and a reference wiring located on second side of the display region. For the first power supply line, data signal line and reference signal line with the same length, resistance of first power supply line is greater than that of the data signal line and that of the reference signal line.

公开(公告)号：US11322713B2

公开(公告)日：2022-05-03

申请号：US16818246

申请日：2020-03-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Pan Xu

IPC: H01L51/52 ,  H01L27/32 ,  H01L51/56

Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes: a backplane; a transistor layer on a side of the backplane; a first planarization layer on a side of the transistor layer away from the backplane; an auxiliary cathode layer on a side of the first planarization layer away from the transistor layer; a second planarization layer on a side of the auxiliary cathode layer away from the first planarization layer; and a light-emitting element layer on a side of the second planarization layer away from the auxiliary cathode layer. The light-emitting element layer includes a primary cathode layer electrically connected to the auxiliary cathode layer.