公开(公告)号：US5986934A

公开(公告)日：1999-11-16

申请号：US977647

申请日：1997-11-24

申请人： Dah-Bin Kao ,  Loc B. Hoang ,  Albert Wu ,  Tung-Yi Chan

发明人： Dah-Bin Kao ,  Loc B. Hoang ,  Albert Wu ,  Tung-Yi Chan

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/28

摘要： A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

摘要翻译： 本文提供了一种半导体存储器阵列及其方法，包括：衬底; 多个存储单元场效应晶体管，形成在所述基板上并被布置在晶体管的行和列中，每个晶体管包括介于漏极和源极区之间并由控制栅极区重叠的沟道区; 形成在所述基板内的多个第一扩散细长区域，其共同地将各个晶体管的漏极区域电连接; 形成在所述衬底内的多个第二扩散细长区域，其共同地将各个晶体管的源极区域电连接; 以及形成在所述衬底上的多个细长导电线，其共同地电连接相应行中的晶体管的控制栅极区域。

公开(公告)号：US5373465A

公开(公告)日：1994-12-13

申请号：US132942

申请日：1993-10-07

申请人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

发明人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  G11C11/34 ,  G11C7/00

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

公开(公告)号：US5317179A

公开(公告)日：1994-05-31

申请号：US764019

申请日：1991-09-23

申请人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

发明人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/68 ,  H01L29/34 ,  H01L29/78

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

摘要翻译： 公开了使用片上电压倍增器电路仅需要5伏外部源的闪速EEPROM单元，以提供在编程和擦除模式期间实现Fowler-Nordheim隧穿所需的高电压。 浮置栅极和控制栅极之间以及浮置栅极和漏极区域之间的介电层的性质不同，以便于浮动栅极的编程和擦除。 还公开了一种通过在浮动栅极和控制栅极之间形成绝缘层以使电容低于浮置栅极和漏极区域之间的绝缘层的电容的电容来产生快闪EEPROM单元的方法。