Electrode structure, array substrate and display device

    公开(公告)号:US11256146B2

    公开(公告)日:2022-02-22

    申请号:US17034063

    申请日:2020-09-28

    Abstract: The application relates to an electrode structure, an array substrate and a display device. The electrode structure has hollow portions, and electrode portions formed between adjacent hollow portions; the hollow portions have first and second hollow holes; projection planes of the first and second hollow holes in the first direction are completely overlapped; the electrode portions comprise: first electrode blocks located between the first hollow holes and second electrode blocks located between the second hollow holes; a sum of widths of each first hollow hole and the first electrode block adjacent to it in the first direction is different from a sum of widths of each second hollow hole and the second electrode block adjacent to it in the first direction; the width is a dimension in the first direction. In this solution, process fluctuations can be reduced and light transmittance can be improved.

    Image processing method and device, storage medium and computer device

    公开(公告)号:US11210765B2

    公开(公告)日:2021-12-28

    申请号:US16300971

    申请日:2018-04-24

    Abstract: An image processing method and device, storage medium and computer device are provided. The method includes: generating an original gray scale image of an original image; performing a histogram equalization process on the original gray scale image to obtain an equalized gray scale image; generating decision factor distribution image, wherein the decision factor distribution image includes a first marked region including a region where pixels that are adjacent in position and have standard deviations smaller than set value in the original image are located, and second marked region; obtaining final gray scale image according to original gray scale image, equalized gray scale image and decision factor distribution image. Gray scale values of pixel corresponding to second marked region and first marked region in final gray scale image are respectively gray scale values of corresponding pixel in equalized gray scale image and original gray scale image; and restoring a processed image.

    Backlight module frame, backlight module, display module, and display device

    公开(公告)号:US11092848B2

    公开(公告)日:2021-08-17

    申请号:US16767148

    申请日:2019-09-18

    Abstract: The disclosure provides a backlight module frame, a backlight module, a display module and a display device. The backlight module frame includes: a middle frame and a fixing member. The middle frame is a hollow frame, and a display panel support stand is disposed on the inner side of the middle frame. The display panel support stand is configured to support a first display panel. The fixing member and the middle frame are detachably connected. When the fixing member is connected to the middle frame, a display panel receiving slot is formed among the display panel support stand, the fixing member and the middle frame. During the transportation of the first display panel, the backlight module frame provided by the present disclosure can protect the first display panel, thereby preventing the display panel from being scratched, and ensuring the display effect of the display device.

    Drive control method, assembly and display device

    公开(公告)号:US11062634B2

    公开(公告)日:2021-07-13

    申请号:US16620408

    申请日:2018-06-04

    Abstract: The disclosure relates to a drive control method and assembly, and a display device. A drive control method for a timing controller includes generating a point-to-point configuration instruction including an identity identification of a source driver, wherein the source driver is any of a plurality of source drivers, sending the point-to-point configuration instruction via first signal lines, and receiving a configuration response instruction sent by the source driver via the one of the first signal lines. The configuration response instruction is sent by the source driver after executing the point-to-point configuration instruction in response to detecting that the identity identification in the instruction is its own identity identification.

    Encoding method and device, decoding method and device, and display device

    公开(公告)号:US11056070B2

    公开(公告)日:2021-07-06

    申请号:US16620168

    申请日:2018-06-01

    Abstract: This application relates to an encoding method and device, a decoding method and device, and a signal transmission system. The encoding method includes: encoding 8-bit data corresponding to a to-be-encoded byte of to-be-transmitted data into 9-bit data, the to-be-transmitted data comprising at least one to-be-encoded byte; detecting the first digit of data of the 9-bit data and a previous digit of data adjacent to the first digit of data, when the to-be-encoded byte is not the first byte of the to-be-transmitted data; inverting the 9-bit data and then adding a tenth digit of data for indicating that the inverted 9-bit data has undergone an inversion operation behind the inverted 9-bit data to obtain 10-bit data, when the numerical value of the first digit of data is the same as that of the previous digit of data; and adding a tenth digit of data for indicating that the 9-bit data has not undergone an inversion operation behind the 9-bit data to obtain 10-bit data, when the numerical value of the first digit of data is different from that of the previous digit of data.

    Shift-register circuit, a driving method thereof, and related display apparatus

    公开(公告)号:US10991332B2

    公开(公告)日:2021-04-27

    申请号:US16614486

    申请日:2018-01-16

    Abstract: The present application discloses a shift-register circuit including a shift-register unit and a shutdown-discharge sub-circuit. The shift-register unit is coupled to a clock port, a first reference voltage port, a second reference voltage port, and an output port and configured to set a voltage level at a pull-up node to control a clock signal from the clock port being outputted to the output port to drive a display panel during a display period. The shutdown discharge sub-circuit is configured to at least simultaneously receive a shutdown signal at a first voltage level from a shutdown-discharge control port and a second signal at the first voltage level from the second reference voltage port to start a shutdown period to discharge at least one of the pull-up node and the output port. The shutdown signal has a signal length longer than a signal length of the second signal.

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