THIN FILM TRANSISTOR, ARRAY SUBSTRATE, FABRICATING METHODS THEREOF, AND DISPLAY APPARATUS

    公开(公告)号:US20210351207A1

    公开(公告)日:2021-11-11

    申请号:US16316112

    申请日:2018-05-14

    Abstract: The present disclosure is related to a thin film transistor. The thin film transistor may include a gate pattern; an active layer pattern; a gate insulating layer between the gate pattern and the active layer pattern; a first conductive pattern including a first pattern part and a first connecting part; a second conductive pattern a second pattern part and a second connecting part; and a first intermediate insulating layer between the first pattern part and the second pattern part. The first conductive pattern and the second conductive pattern may be a source pattern and a drain pattern, respectively. A first through hole may be provided on the first intermediate insulating layer. The second conductive pattern may be connected to the active layer pattern through the second connecting part in the first through hole.

    Pixel circuit having latch sub-circuit and latch-control sub-circuits, display panel, driving method thereof, and a display apparatus

    公开(公告)号:US11074883B2

    公开(公告)日:2021-07-27

    申请号:US16616956

    申请日:2017-12-13

    Inventor: Fuqiang Li Jun Fan

    Abstract: The present application discloses a pixel circuit of a display panel. The pixel circuit includes a first latch-control sub-circuit configured to provide a data signal under controls of a first scan signal, a latch sub-circuit including a first inverter having an input terminal coupled to receive the data signal and a second inverter, a second latch-control sub-circuit configured to disconnect the second inverter from the first inverter to form an open circuit under controls of the first scan signal or form a latch loop under controls of a second scan signal to stabilize two voltage levels at the first output terminal of the first inverter and the second output terminal of the second output inverter, and an output sub-circuit configured to switch connection between an output terminal and two reference voltage ports under controls of the two voltage levels alternatively.

    Shift register unit circuit, driving method thereof, gate drive circuit and display device

    公开(公告)号:US10706767B2

    公开(公告)日:2020-07-07

    申请号:US15756975

    申请日:2017-08-31

    Abstract: A shift register unit circuit includes an input circuit configured to supply an active potential to a first node responsive to an input pulse from an input terminal being active and to supply an inactive potential to the first node responsive to a reset pulse from a reset terminal being active; an output circuit configured to supply a first clock signal to an output terminal responsive to a second node being at the active potential and to cause a potential at the second node to be changed from the active potential to further away from the inactive potential responsive to a transition of a potential at the output terminal transitioning from the inactive potential to the active potential; and a potential control circuit configured to restrict a change in the potential at the first node caused by the transition of the potential at the output terminal from the inactive potential to the active potential.

    Array substrate, method for manufacturing the same, display device and mask plate

    公开(公告)号:US10283536B2

    公开(公告)日:2019-05-07

    申请号:US15325623

    申请日:2016-07-22

    Inventor: Fuqiang Li

    Abstract: A method for manufacturing an array substrate includes (S1) forming a pattern including a gate electrode and a gate line, (S2) forming an insulating layer, (S3) forming a pattern including an active layer, where the region where the active layer is arranged includes a first region corresponding to the gate electrode and second regions arranged on both sides of the first region, (S4) forming a mask pattern including a hollowed-out portion, a first portion and a second portion, wherein the second portion has a thickness smaller than the first portion, (S5) etching the insulating layer to form a via hole for exposing a portion of the gate line, and (S6) ashing a portion of the mask pattern corresponding to the second region to remove the portion of the mask pattern corresponding to the second region, and implanting ions into the active layer.

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