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公开(公告)号：US08315298B2
公开(公告)日：2012-11-20
申请号：US11930780
申请日：2007-10-31
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/0262 , H04L2025/03547
摘要： Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).
摘要翻译： 提供了用于均衡接收信号的方法和装置。 接收到的信号通过确定接收信号的数据速率来均衡; 获得与所确定的数据速率相关联的一个或多个均衡参数; 以及使用所获得的一个或多个均衡参数来均衡所接收的信号。 均衡参数可以包括例如增益参数，高通滤波器的零控制和在均衡步骤期间使用的一个或多个锁存器的一个或多个阈值设置中的一个或多个，诸如数据锁存器或转换锁存器（或 都）。
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92.发明授权Methods and apparatus for detecting a loss of lock condition in a clock and data recovery system 有权用于检测时钟和数据恢复系统中锁定状况的损失的方法和装置公开(公告)号：US08208521B2
公开(公告)日：2012-06-26
申请号：US11967632
申请日：2007-12-31
IPC分类号： H04B17/00
CPC分类号： H04L7/0062 , H04L7/0083
摘要： Methods and apparatus are provided for detecting a loss of lock condition in a clock and data recovery system. A loss of lock condition is detected in a clock and data recovery system that generates a recovered clock signal from a received signal by sampling the received signal for a plurality of different phases using one or more latches clocked by the recovered clock; evaluating the samples to monitor a data eye associated with the received signal; and detecting the loss of lock condition if the data eye does not satisfy one or more predefined conditions. Generally, the predefined conditions identify a loss of the data eye (e.g., when the data eye cannot be substantially detected), for example, based on a degree of opening of the data eye. The clock and data recovery system can optionally be restarted if the loss of lock condition is detected.
摘要翻译： 提供了用于检测时钟和数据恢复系统中的锁定状况的损失的方法和装置。 在时钟和数据恢复系统中检测到锁定状态的损失，该系统通过使用由恢复时钟计时的一个或多个锁存器对接收到的信号进行多个不同相位的采样来产生来自接收信号的恢复时钟信号; 评估样本以监测与接收信号相关联的数据眼; 并且如果数据眼不满足一个或多个预定条件，则检测锁定条件的损失。 通常，预定义的条件识别数据眼睛的损失（例如，当不能基本上检测到数据眼时），例如，基于数据眼睛的打开程度。 如果检测到锁定状态的丢失，则可以重新启动时钟和数据恢复系统。
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公开(公告)号：US08046481B2
公开(公告)日：2011-10-25
申请号：US12610462
申请日：2009-11-02
IPC分类号： G06F15/16
CPC分类号： H04L12/2838 , H04L69/03 , H04L69/32
摘要： A conventional serial communications protocol that is limited to supporting only host-to-slave communications, such as SATA or SAS, is extended to support peer-to-peer communications, e.g., by adding a memory-map layer into the conventional protocol stack between the link layer and the protocol layer. The addition of the memory-map layer enables two (or more) non-host devices (i.e., peer devices) to communicate with one another without using a host computer and without relying on conventional protocol-bridging techniques.
摘要翻译： 仅限于支持诸如SATA或SAS的主机到从机通信的常规串行通信协议被扩展以支持对等通信，例如通过将存储器映射层添加到常规协议栈之间 链路层和协议层。 存储器映射图层的添加使得两个（或多个）非主机设备（即，对等设备）彼此通信，而不使用主计算机，而不依赖于传统的协议桥接技术。
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94.发明授权公开(公告)号：US07995743B2
公开(公告)日：2011-08-09
申请号：US11534918
申请日：2006-09-25
IPC分类号： H04M3/00
CPC分类号： H04M3/2272 , H04M3/14
摘要： The invention provides a low cost, simple, circuit for detecting the condition of a telephone line.
摘要翻译： 本发明提供了一种用于检测电话线条件的低成本，简单的电路。
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95.发明授权公开(公告)号：US07923868B2
公开(公告)日：2011-04-12
申请号：US12012761
申请日：2008-02-05
IPC分类号： H02J3/00
CPC分类号： H03K19/0027 , G06F1/3203 , H03K19/00384 , Y10T307/74
摘要： Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.
摘要翻译： 公开了一种被配置为向开关元件（例如，晶体管）施加电源电压的电路。 该电路包括一个锁存器和一个处理器。 锁存器被配置为对开关元件的输出信号的电压进行采样，并且处理器被配置为产生功率调整信号，以基于由锁存器采样的电压来调节电源电压。
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96.发明授权Method and apparatus for decision-feedback equalization using single-sided eye with global minimum convergence 有权使用具有全局最小收敛的单面眼的判决反馈均衡的方法和装置公开(公告)号：US07720142B2
公开(公告)日：2010-05-18
申请号：US11686148
申请日：2007-03-14
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： Methods and apparatus are provided for decision-feedback equalization with global minimum convergence. A threshold position of one or more DFE latches employed by a decision-feedback equalizer is determined by obtaining a plurality of samples of a single-sided data eye using at least one decision latch and at least one roaming latch; comparing the samples obtained by the at least one decision latch and at least one roaming latch to identify an upper and lower voltage boundary of the single-sided data eye; and determining a threshold position of the one or more DFE latches based on the upper and lower voltage boundaries. The comparison can optionally comprise obtaining an exclusive or (XOR) of the samples obtained by the at least one decision latch and at least one roaming latch. The XOR comparison positions an opening for the single-sided data eye at a zero hit count.
摘要翻译： 提供了用于具有全局最小收敛的判决反馈均衡的方法和装置。 通过使用至少一个判定锁存器和至少一个漫游锁存器获得单面数据眼睛的多个采样来确定由判决反馈均衡器采用的一个或多个DFE锁存器的阈值位置; 将由所述至少一个判定锁存器获得的样本和至少一个漫游锁存器进行比较，以识别所述单侧数据眼睛的上下电压边界; 以及基于所述上下电压边界确定所述一个或多个DFE锁存器的阈值位置。 比较可以可选地包括获得由至少一个决定锁存器和至少一个漫游锁存器获得的样本的异或（XOR）。 XOR比较将零点击数的单面数据眼的开口位置。
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97.发明授权公开(公告)号：US07696800B2
公开(公告)日：2010-04-13
申请号：US12012758
申请日：2008-02-05
IPC分类号： H03K5/12
CPC分类号： H03K5/02 , H03K5/06 , H03K19/017581 , H04L25/0288
摘要： Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.
摘要翻译： 公开了一种通过通信信道（例如，线，背板等）调整从发射机发射到接收机的信号的特性的电路。 该电路包括一个锁存器，该锁存器在阈值电压施加到锁存器之后多次接收电路中预定点处的信号并对信号的电压进行多次采样。 该电路还包括一个处理器，当采样电压指示转换点时，确定信号的特性，并且当采样电压不指示转换点时调整阈值电压。 当信号的特性在预定范围之外时，处理器通过调节发射机的电流和电压中的至少一个来调整信号的特性。
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公开(公告)号：US07657799B2
公开(公告)日：2010-02-02
申请号：US11418401
申请日：2006-05-04
IPC分类号： G01R31/28
CPC分类号： G06F11/221
摘要： Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first operational mode of the interface and operable during a second operational mode of the interface. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.
摘要翻译： 公开了用于测试双模式接口的系统和方法。 双模式接口包括第一选通电路和第二选通电路，其被配置为在接口的第一操作模式期间不可操作并且可在接口的第二操作模式期间操作。 双模式接口还包括第一数据电路和第二数据电路，其被配置为在第一操作模式和第二操作模式期间可操作。 双模式接口还包括将第二选通电路的输出与第一选通电路的输入连接的信号线和被配置为响应于接收到测试信号而激活所述信号线的开关元件。
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99.发明授权Method and apparatus for non-linear decision-feedback equalization in the presence of asymmetric channel 有权在存在非对称信道的情况下进行非线性判决反馈均衡的方法和装置公开(公告)号：US07606302B2
公开(公告)日：2009-10-20
申请号：US11541379
申请日：2006-09-29
CPC分类号： H04L25/03057 , H04B10/695
摘要： Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization in the presence of a non-linear channel. A latch employed by a decision-feedback equalizer is positioned by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; determining a threshold position of the latch based on the samples; and transforming the determined position to address the non-linearity of the channel. For example, a non-linear mapping table can map measured threshold values to transformed threshold values based on distance.
摘要翻译： 提供了用于在存在非线性通道的情况下确定用于判决反馈均衡的一个或多个锁存器的阈值位置的方法和装置。 由判决反馈均衡器采用的锁存器通过约束输入数据来定位，使得输入数据仅包含来自第一二进制值的转换; 获得与所述约束输入数据相关联的单面数据眼睛的多个样本; 基于所述样本确定所述锁存器的阈值位置; 并且变换确定的位置以解决信道的非线性。 例如，非线性映射表可以将测量的阈值映射到基于距离的变换的阈值。
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公开(公告)号：US07560957B2
公开(公告)日：2009-07-14
申请号：US11421675
申请日：2006-06-01
申请人： Jinghong Chen , Gregory W. Sheets , Lane A. Smith
发明人： Jinghong Chen , Gregory W. Sheets , Lane A. Smith
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175 , H03K19/20 , H03K19/094
CPC分类号： H03K19/09432 , H03K19/01707
摘要： A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.
摘要翻译： 提供了一种电流模式逻辑数字电路，包括具有至少一个数据输入节点和至少一个输出节点的逻辑电路组件。 负载耦合在电源节点和输出节点之间。 负载包括耦合到输出节点的折叠有源电感器。
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