公开(公告)号：US20110122700A1

公开(公告)日：2011-05-26

申请号：US13018026

申请日：2011-01-31

Applicant: Lyle D. Jones ,  Roger W. Lindsay ,  Kirk D. Prall

Inventor： Lyle D. Jones ,  Roger W. Lindsay ,  Kirk D. Prall

IPC: G11C16/04

CPC classification number: H01L27/115 ,  G11C5/02 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11524

Abstract: A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to the first active area string and to the second active area string. The relaxed metal pitch architecture may be applied to a non-volatile memory structure.

Abstract translation: 轻松的金属间距结构可以包括位线和第一有效区域串和第二有效区域串。 位线可以直接耦合到第一有效区域串和第二有效区域串。 轻松的金属间距结构可以应用于非易失性存储器结构。

公开(公告)号：US20100267240A1

公开(公告)日：2010-10-21

申请号：US12827506

申请日：2010-06-30

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L21/302 ,  C23F1/08

CPC classification number: H01L21/67063 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32053 ,  H01L21/32134

Abstract: Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.

Abstract translation: 在不执行间隔物蚀刻的情况下形成间距倍增过程中的间隔物。 相反，心轴形成在衬底上，然后心轴的侧面例如在氧化，氮化或硅化步骤中反应，以形成相对于心轴的未反应部分可以选择性去除的材料。 选择性地去除未反应部分以留下独立间隔物的图案。 独立的间隔物可以用作后续处理步骤的掩模，例如蚀刻基底。

公开(公告)号：US07776744B2

公开(公告)日：2010-08-17

申请号：US11219346

申请日：2005-09-01

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/67063 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32053 ,  H01L21/32134

Abstract: Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.

Abstract translation: 在不执行间隔物蚀刻的情况下形成间距倍增过程中的间隔物。 相反，心轴形成在衬底上，然后心轴的侧面例如在氧化，氮化或硅化步骤中反应，以形成相对于心轴的未反应部分可以选择性去除的材料。 选择性地去除未反应部分以留下独立间隔物的图案。 独立的间隔物可以用作后续处理步骤的掩模，例如蚀刻基底。

公开(公告)号：US07750389B2

公开(公告)日：2010-07-06

申请号：US11346421

申请日：2006-02-02

Applicant: Kirk D. Prall ,  Leonard Forbes

Inventor： Kirk D. Prall ,  Leonard Forbes

IPC: H01L29/72

CPC classification number: H01L27/11568 ,  G11C11/5692 ,  G11C16/0475 ,  H01L27/115

Abstract: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

Abstract translation: 配置为存储每个F2的至少一个位的存储器单元的阵列包括基本上垂直的结构，提供间隔距离等于阵列的最小间距的一半的距离的电子存储器功能。 提供电子存储器功能的结构被配置为存储每个门多于一个位。 阵列还包括到存储器单元的电接触，包括基本垂直的结构。 电池可以被编程为具有与栅极绝缘体相邻的多个电荷水平中的一个，其邻近于第一源极/漏极区域，使得沟道区域具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2） 并且使得编程单元以降低的漏极源电流工作。

公开(公告)号：US20100142273A1

公开(公告)日：2010-06-10

申请号：US12699658

申请日：2010-02-03

Applicant: CHUN CHEN ,  Kirk D. Prall

Inventor： CHUN CHEN ,  Kirk D. Prall

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0483

Abstract: A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.

Abstract translation: 提供了一种用于对存储单元进行编程的方法。 存储单元制造在衬底上，并且包括源极区域，漏极区域，浮动栅极和控制栅极。 存储单元具有可选地配置为至少三个编程状态之一的阈值电压。 该方法包括通过在漏极区域和源极区域之间施加漏极 - 源极偏置电压来在漏极区域和源极区域之间产生漏极电流。 该方法还包括通过向控制栅极施加栅极电压将热电子从漏极电流注入到浮置栅极。 通过施加不同的选择的栅极电压来产生对应于选择的一个编程状态的存储单元的选定的阈值电压。

公开(公告)号：US07684249B2

公开(公告)日：2010-03-23

申请号：US11496969

申请日：2006-08-01

Applicant: Chun Chen ,  Kirk D. Prall

Inventor： Chun Chen ,  Kirk D. Prall

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0483

Abstract: A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.

Abstract translation: 提供了一种用于对存储器单元进行编程的方法。 存储单元制造在衬底上，并且包括源极区域，漏极区域，浮动栅极和控制栅极。 存储单元具有可选地配置为至少三个编程状态之一的阈值电压。 该方法包括通过在漏极区域和源极区域之间施加漏极 - 源极偏置电压来在漏极区域和源极区域之间产生漏极电流。 该方法还包括通过向控制栅极施加栅极电压将热电子从漏极电流注入到浮置栅极。 通过施加不同的选择的栅极电压来产生对应于选择的一个编程状态的存储单元的选定的阈值电压。

公开(公告)号：US07651911B2

公开(公告)日：2010-01-26

申请号：US11648200

申请日：2006-12-29

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7885 ,  H01L29/792

Abstract: A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.

Abstract translation: 形成存储晶体管的方法包括提供包括半导体材料并形成间隔开的源极/漏极结构的衬底。 源极/漏极结构中的至少一个与半导体材料形成肖特基接触。 该方法还包括在间隔开的源极/漏极结构之间形成存储栅极，并形成可操作地设置在存储器栅极上的控制栅极。

公开(公告)号：US20090263962A1

公开(公告)日：2009-10-22

申请号：US12496437

申请日：2009-07-01

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L21/28 ,  H01L21/311

CPC classification number: H01L29/7881 ,  B82Y10/00 ,  G11C16/0408 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/513

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.

Abstract translation: 一种制造存储单元的方法，包括在第一介电层上形成纳米点，并在纳米点上形成第二介电层，其中第二介电层包裹纳米点。 此外，在第二介电层上形成隔间电介质层。 为了形成存储器单元的侧壁，间隔电介质层的一部分和第二电介质层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对第二介电层选择性的各向同性蚀刻去除第二介电层和纳米点的剩余部分。

公开(公告)号：US20080121976A1

公开(公告)日：2008-05-29

申请号：US11513933

申请日：2006-08-31

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L29/788 ,  H01L21/04 ,  H01L29/68 ,  G11C11/34

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L29/42332

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.

Abstract translation: 一种制造存储单元的方法，包括在第一介电层上形成纳米点并在纳米点上形成隔间电介质层，其中隔间电介质层封装在纳米点上。 为了形成存储器单元的侧壁，隔离介电层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对栅极间电介质层选择性的蚀刻来去除间隔栅电介质层和纳米点的剩余部分。

公开(公告)号：US07157305B2

公开(公告)日：2007-01-02

申请号：US11392290

申请日：2006-03-29

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L21/00

CPC classification number: G11C16/04

Abstract: A method of forming a memory array includes forming a stack of two or more layers of memory material on a substrate, each layer of memory material having an array of memory cells, and forming one or more contacts that pass through each of the layers of memory material.

Abstract translation: 形成存储器阵列的方法包括在衬底上形成两层或更多层存储材料的堆叠，每层存储器材料具有存储器单元阵列，并且形成穿过存储器层中的每一层的一个或多个触点 材料。