公开(公告)号：US4586171A

公开(公告)日：1986-04-29

申请号：US381584

申请日：1982-05-24

Applicant: Kazuyasu Fujishima

Inventor： Kazuyasu Fujishima

IPC: G11C11/401 ,  G11C7/02 ,  G11C11/404 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC classification number: G11C11/404 ,  G11C11/4097

Abstract: A random access type semiconductor memory comprises a plurality of word lines (44; 54) of a metal arranged in parallel, at least first to fourth bit lines (BL1, BL2, BL1, BL2) orthogonal to the word lines, a plurality of memory cells (48; 58a, 58b), each of which is arranged corresponding to one of cross points between each of the word lines and each of the bit lines, a first sense amplifier (SA1) connected to the first and third bit lines (BL1, BL1) and a second sense amplifier (SA2) connected to the second and fourth bit lines (BL2, BL2). The first sense amplifier (SA1) amplifies a voltage applied to said first or third bit line from a selected first memory cell and the second sense amplifier (SA2) amplifies a voltage applied to the second or fourth bit line from a selected second memory cell.

Abstract translation: 随机存取型半导体存储器包括与字线正交的至少第一至第四位线（BL1，BL2，BL1，BL2）并行布置的金属的多个字线（44; 54），多个存储器 单元（48; 58a，58b），每个单元对应于每个字线和每个位线之间的交叉点之一布置;第一读出放大器（SA1），连接到第一和第三位线（BL1 ，BL1）和连接到第二和第四位线（BL2，BL2）的第二读出放大器（SA2）。 第一读出放大器（SA1）放大从所选择的第一存储单元施加到所述第一或第三位线的电压，并且第二读出放大器（SA2）放大从所选择的第二存储器单元施加到第二或第四位线的电压。

公开(公告)号：US4456939A

公开(公告)日：1984-06-26

申请号：US261298

申请日：1981-05-07

Applicant: Hideyuki Ozaki ,  Kazuyasu Fujishima

Inventor： Hideyuki Ozaki ,  Kazuyasu Fujishima

IPC: H03K17/08 ,  H03K17/0812 ,  H02H3/20

CPC classification number: H03K17/08122 ,  H01L2924/0002

Abstract: An input protective circuit of MIS type device is used by applying reverse bias voltage to a semiconductor substrate and a variable-conductivity element is connected between the input terminal of the MIS type device and the ground so that the input terminal is in conductive state to the ground when the reverse bias voltage is not applied to the semiconductor substrate and the input terminal is in non-conductive state to the ground when the reverse bias voltage is applied to the semiconductor substrate.

Abstract translation: 通过向半导体衬底施加反向偏压来使用MIS型器件的输入保护电路，并且可变导电元件连接在MIS型器件的输入端子与地之间，使得输入端子处于导通状态 当反向偏置电压施加到半导体衬底时，当反向偏置电压未施加到半导体衬底并且输入端子处于非导通状态时，接地。

公开(公告)号：US4243897A

公开(公告)日：1981-01-06

申请号：US901258

申请日：1978-04-28

Applicant: Kazuyasu Fujishima ,  Michihiro Yamada ,  Kouichi Nagasawa

Inventor： Kazuyasu Fujishima ,  Michihiro Yamada ,  Kouichi Nagasawa

IPC: G11C27/04 ,  G11C19/28 ,  G11C19/36 ,  H01L21/339 ,  H01L29/417 ,  H01L29/762 ,  H01L29/768 ,  H01L29/78

CPC classification number: G11C19/285 ,  G11C19/36 ,  H01L29/76808

Abstract: The single input gate electrode in a conventional CCD shift register is replaced by four spaced electrodes. The fourth electrode adjacent to the first transfer electrode has an area larger than that of the second electrode which always has a DC voltage applied thereto. Three driving pulses are applied in a predetermined sequence to the first, third and fourth electrodes while the two bit values of 2-bit information are written into the register and a charge is accumulated directly under the fourth input gate electrode at one of four levels as determined by the combination of the write bit values. Then the accumulated charge is stepwise transferred in the same manner as in conventional CCD shift registers.

Abstract translation: 常规CCD移位寄存器中的单输入栅电极由四个隔开的电极代替。 与第一转印电极相邻的第四电极的面积大于施加有直流电压的第二电极的面积。 将三个驱动脉冲以预定的顺序施加到第一，第三和第四电极，同时将2位信息的两个位值写入寄存器，并且在四级输入栅极之前直接在第四输入栅电极下积累电荷， 由写位值的组合决定。 然后以与常规CCD移位寄存器相同的方式逐步传送累积电荷。