公开(公告)号：US20180234060A1

公开(公告)日：2018-08-16

申请号：US15811860

申请日：2016-06-08

Applicant: Intel IP Corporation

Inventor： Andreas Langer ,  Christoph Hepp

IPC: H03F3/19 ,  H03F3/24 ,  H03F1/02 ,  H03G3/30

CPC classification number: H03F3/19 ,  H03F1/0216 ,  H03F1/0222 ,  H03F3/245 ,  H03F2200/105 ,  H03F2200/336 ,  H03F2200/36 ,  H03F2200/451 ,  H03G3/3042 ,  H03G2201/302 ,  H03G2201/307 ,  H04B1/04

Abstract: A circuit for generating a radio frequency signal is provided. The circuit includes an amplifier configured to generate a radio frequency signal based on a baseband signal. Further, the circuit includes a power supply configured to generate a variable supply voltage based on a control signal indicating a desired supply voltage, and to supply the variable supply voltage to the amplifier. The circuit further includes an envelope tracking circuit configured to generate the control signal based on a bandwidth of the baseband signal, and to supply the control signal to the power supply.

公开(公告)号：US20120129478A1

公开(公告)日：2012-05-24

申请号：US13299581

申请日：2011-11-18

Applicant: Henk Ten Pierick ,  Gertjan Groot Hulze ,  Erik Keukens

Inventor： Henk Ten Pierick ,  Gertjan Groot Hulze ,  Erik Keukens

IPC: H04B1/16 ,  H03G3/20

CPC classification number: H03G3/3052 ,  H03G3/301 ,  H03G2201/202 ,  H03G2201/302 ,  H03G2201/606

Abstract: An automatic gain control circuit is provided for an input signal in the form of a dc reference level and a superposed amplitude modulated ac data signal. A feedforward AGC loop has a low pass filter for deriving the level of attenuation from the attenuated dc reference level. A multiplier value (G) is based on the reciprocal of the level of attenuation (α) and this multiplier enables an output signal to be generated comprising a constant multiple (DG) of the input signal.

Abstract translation: 为直流基准电平和重叠幅度调制交流数据信号形式的输入信号提供自动增益控制电路。 前馈AGC环路具有用于从衰减的直流参考电平导出衰减电平的低通滤波器。 乘法器值（G）基于衰减电平（α）的倒数，并且该乘法器使得能够产生包括输入信号的恒定倍数（DG）的输出信号。

公开(公告)号：US20180287647A1

公开(公告)日：2018-10-04

申请号：US15924717

申请日：2018-03-19

Applicant: Panasonic Corporation

Inventor： YOHEI MORISHITA ,  TAKENORI SAKAMOTO

IPC: H04B1/16 ,  H03G3/30

CPC classification number: H04B1/16 ,  H03G3/3042 ,  H03G3/3052 ,  H03G3/3078 ,  H03G2201/302 ,  H03G2201/307 ,  H04B1/0028

Abstract: A gain controller sets a gain code indicating an optimum gain, a cutoff frequency code indicating a cutoff frequency, and a number of bits code indicating a number of bits. An AEQ/VGA gain controller sets a frequency characteristic code indicating a frequency characteristic, a gain code indicating a gain after correction, and a number of bits code indicating a number of bits. An AEQ/VGA amplifies a baseband received signal on the basis of a gain code and corrects a frequency characteristic of the baseband received signal on the basis of a frequency characteristic code. An HPF cuts off a band below a cutoff frequency of an output signal from the AEQ/VGA on the basis of a cutoff frequency code. An ADC quantizes an output signal from the HPF using a number of bits based on a number of bits code and generates a digital received signal.

公开(公告)号：US07212795B2

公开(公告)日：2007-05-01

申请号：US10864193

申请日：2004-06-09

Applicant: Der-Zheng Liu ,  Song-Nien Tang ,  Tai-Cheng Liu ,  Kuang-Yu Yen

Inventor： Der-Zheng Liu ,  Song-Nien Tang ,  Tai-Cheng Liu ,  Kuang-Yu Yen

IPC: H04B1/06

CPC classification number: H03G3/3052 ,  H03G2201/206 ,  H03G2201/302 ,  H03G2201/305 ,  H03G2201/307 ,  H03G2201/502 ,  H03G2201/508 ,  H03M1/185 ,  H04B7/0814

Abstract: The invention provides an automatic gain control and antenna selection method used in a receiver of a radio communication system. The received signal power is estimated by digital signal processing after analog-to-digital conversion in the system, in order to adjust the gain of the front end analog signal until the magnitude of the analog signal is adjusted to an optimum range of the digital signal processing. In addition, the ADC is utilized to estimate the signal power as the basis of the antenna selection.

Abstract translation: 本发明提供一种在无线电通信系统的接收机中使用的自动增益控制和天线选择方法。 接收到的信号功率通过系统中模数转换后的数字信号处理来估计，以便调整前端模拟信号的增益，直到模拟信号的幅度被调整到数字信号的最佳范围 处理。 此外，ADC用于估计信号功率作为天线选择的基础。

公开(公告)号：US20170294889A1

公开(公告)日：2017-10-12

申请号：US15480097

申请日：2017-04-05

Applicant: NXP USA, Inc.

Inventor： Cristian Pavao-Moreira ,  Rex Kenton Hales

IPC: H03G3/30 ,  H03F3/45 ,  H03F3/72 ,  H03F3/19

CPC classification number: H03G3/3036 ,  G01S13/0209 ,  H03F3/19 ,  H03F3/45094 ,  H03F3/72 ,  H03F2200/384 ,  H03F2200/411 ,  H03F2200/456 ,  H03F2200/69 ,  H03F2203/45061 ,  H03F2203/45081 ,  H03F2203/45112 ,  H03F2203/7221 ,  H03G3/3052 ,  H03G2201/302 ,  H03G2201/40 ,  H03K19/018585

Abstract: A device includes a variable gain amplifier, a voltage shifter, a variable gain amplifier half replica module, and an analog to digital converter. The variable gain amplifier includes an input terminal to receive an input signal, an output terminal to provide a first output signal that is biased based on a first common-mode voltage reference. The voltage shifter circuit includes first and second input terminals, and an output terminal to provide, to the analog to digital converter, a third output signal that is biased based on a second common-mode voltage reference. The variable gain amplifier half replica module includes an output terminal coupled to the second input terminal of the voltage shifter circuit, the variable gain amplifier half replica module to control the third output signal of the voltage shifter circuit based on the first common-mode voltage reference and the second common-mode voltage reference.

公开(公告)号：US08559903B2

公开(公告)日：2013-10-15

申请号：US13299581

申请日：2011-11-18

Applicant: Henk Ten Pierick ,  Gertjan Groot Hulze ,  Erik Keukens

Inventor： Henk Ten Pierick ,  Gertjan Groot Hulze ,  Erik Keukens

IPC: H04B1/06 ,  H04B7/00

CPC classification number: H03G3/3052 ,  H03G3/301 ,  H03G2201/202 ,  H03G2201/302 ,  H03G2201/606

Abstract: An automatic gain control circuit is provided for an input signal in the form of a dc reference level and a superposed amplitude modulated ac data signal. A feedforward AGC loop has a low pass filter for deriving the level of attenuation from the attenuated dc reference level. A multiplier value (G) is based on the reciprocal of the level of attenuation (α) and this multiplier enables an output signal to be generated comprising a constant multiple (DG) of the input signal.

Abstract translation: 为直流基准电平和重叠幅度调制交流数据信号形式的输入信号提供自动增益控制电路。 前馈AGC环路具有用于从衰减的直流参考电平导出衰减电平的低通滤波器。 乘数值（G）基于衰减电平（α）的倒数，并且该乘法器使得能够产生包括输入信号的恒定倍数（DG）的输出信号。

公开(公告)号：US08050367B2

公开(公告)日：2011-11-01

申请号：US12066877

申请日：2006-09-14

Applicant: Masaki Ichihara

Inventor： Masaki Ichihara

IPC: H04L27/08

CPC classification number: H03G3/3089 ,  H03G3/001 ,  H03G3/3052 ,  H03G2201/302 ,  H04B1/30

Abstract: Input average levels and output average levels of digital channel filters 217 and 218 are computed in amplitude calculation circuits 101 and 102. In a gain difference calculation circuit 103, a gain difference of the input levels and the output levels is computed as a multiplier α so that a difference between the input levels and the output levels are eliminated or adjusted to be within a certain value. The outputs of the digital channel filters 217 and 218 are multiplied by the multiplier α in multiplier units 104 and 105. The multiplication results are outputted as corrected digital signals to a subsequent digital signal processing circuit.

Abstract translation: 在幅度计算电路101和102中计算数字通道滤波器217和218的输入平均电平和输出平均电平。在增益差计算电路103中，输入电平和输出电平的增益差被计算为乘数α，因此 输入电平和输出电平之间的差异被消除或调整到一定值之内。 数字信道滤波器217和218的输出在乘法器单元104和105中乘以乘法器α。乘法结果作为经校正的数字信号输出到随后的数字信号处理电路。

公开(公告)号：US20050129150A1

公开(公告)日：2005-06-16

申请号：US11007159

申请日：2004-12-09

Applicant: Kenji Terao

Inventor： Kenji Terao

IPC: H03G3/20 ,  H03G3/30 ,  H04B1/16 ,  H04B1/30 ,  H04B1/707 ,  H04B1/7097 ,  H03D1/00

CPC classification number: H03G3/3078 ,  H03G3/3068 ,  H03G2201/103 ,  H03G2201/202 ,  H03G2201/302 ,  H03G2201/307

Abstract: In a slot format of a received signal, AGC gain update timings (t1 to t4) are shifted every time to disperse and reduce an influence of a noise attributable to a direct current component specific to direct conversion which is accompanied by AGC gain update. In particular, in the case where each of slots in the received signal includes an information portion (data) having a larger code correcting capability and an information portion having a smaller code correcting capability (TPC (transmission power control), TFCI (transport format combination indicator), PILOT), the AGC gain update timing is generated while being shifted in the former information portion, thereby reduce the influence of the noise. When the amount of shift of the AGC gain update timing is set to be larger than that of one symbol of the received signal, the influence of the noise accompanied by the AGC gain update is further reduced.

Abstract translation: 在接收信号的时隙格式中，AGC增益更新定时（t 1至t 4）每次都被移位以分散并减小归因于直接转换的特定于直流转换的直流分量的噪声的影响，伴随着AGC增益更新 。 特别地，在接收信号中的每个时隙包括具有较大代码校正能力的信息部分（数据）和具有较小代码校正能力的信息部分（TPC（传输功率控制）），TFCI（传输格式组合 指示器），PILOT）时，在前一个信息部分中移动时产生AGC增益更新定时，从而减少噪声的影响。 当AGC增益更新定时的移位量被设置为大于接收信号的一个符号的移位量时，进一步降低伴随AGC增益更新的噪声的影响。

公开(公告)号：US20040162104A1

公开(公告)日：2004-08-19

申请号：US10713613

申请日：2003-11-14

Applicant: InterDigital Technology Corporation

Inventor： Fatih Ozluturk ,  Leonid Kazakevich ,  Kenneth P. Kearney ,  Geetha Lakshmi Narayan ,  Alpaslan Demir ,  Tanbir Haque

IPC: H04B001/40 ,  H04B017/00 ,  H04B001/06 ,  H04B007/00

CPC classification number: H03G3/001 ,  H03D3/008 ,  H03D3/009 ,  H03G3/3068 ,  H03G3/3089 ,  H03G2201/103 ,  H03G2201/202 ,  H03G2201/302 ,  H03G2201/307 ,  H03G2201/508 ,  H04B1/30 ,  H04L2027/0016 ,  H04L2027/0024

Abstract: In order to compensate for performance degradation caused by inferior low-cost analog radio component tolerances of an analog radio, a future system architecture (FSA) wireless communication transceiver employs numerous digital signal processing (DSP) techniques to compensate for deficiencies of such analog components so that modern specifications may be relaxed. Automatic gain control (AGC) functions are provided in the digital domain, so as to provide enhanced phase and amplitude compensation, as well as many other radio frequency (RF) parameters.

Abstract translation: 为了补偿由模拟无线电的低成本模拟无线电组件公差引起的性能下降，未来的系统架构（FSA）无线通信收发器采用多种数字信号处理（DSP）技术来补偿这种模拟组件的缺陷， 现代规格可能放宽。 在数字域中提供自动增益控制（AGC）功能，以提供增强的相位和幅度补偿以及许多其他射频（RF）参数。

公开(公告)号：US20090285340A1

公开(公告)日：2009-11-19

申请号：US12066877

申请日：2006-09-14

Applicant: Masaki Ichihara

Inventor： Masaki Ichihara

IPC: H04L27/08

CPC classification number: H03G3/3089 ,  H03G3/001 ,  H03G3/3052 ,  H03G2201/302 ,  H04B1/30

Abstract: Input average levels and output average levels of digital channel filters 217 and 218 are computed in amplitude calculation circuits 101 and 102. In a gain difference calculation circuit 103, a gain difference of the input levels and the output levels is computed as a multiplier α so that a difference between the input levels and the output levels are eliminated or adjusted to be within a certain value. The outputs of the digital channel filters 217 and 218 are multiplied by the multiplier α in multiplier units 104 and 105. The multiplication results are outputted as corrected digital signals to a subsequent digital signal processing circuit.

Abstract translation: 在幅度计算电路101和102中计算数字信道滤波器217和218的输入平均电平和输出平均电平。在增益差计算电路103中，输入电平和输出电平的增益差被计算为乘数α 输入电平和输出电平之间的差异被消除或调整到一定值之内。 数字通道滤波器217和218的输出乘以乘法器单元104和105中的乘法器α。乘法结果作为经校正的数字信号输出到随后的数字信号处理电路。