知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.017 seconds)

    Embedded transistor
    1.
    发明授权
    Embedded transistor 有权
    嵌入式晶体管

    公开(公告)号：US08853021B2

    公开(公告)日：2014-10-07

    申请号：US13273012

    申请日：2011-10-13

    Applicant: Yu-Wei Ting ,  Kuo-Ching Huang

    Inventor： Yu-Wei Ting ,  Kuo-Ching Huang

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L27/108

    CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/66621 ,  H01L29/78

    Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell.

    Abstract translation: 提供了一种用于电气设备的嵌入式晶体管，例如DRAM存储单元及其制造方法。 在衬底中形成沟槽，并且在衬底的沟槽中形成栅极电介质和栅电极。 源极/漏极区域形成在沟槽的相对侧上的衬底中。 在一个实施例中，源极/漏极区域中的一个耦合到存储节点，而另一个源极/漏极区域耦合到位线。 在该实施例中，栅电极可以耦合到字线以形成DRAM存储单元。

    Method of forming an embedded memory device
    3.
    发明授权
    Method of forming an embedded memory device 有权
    形成嵌入式存储器件的方法

    公开(公告)号：US09082705B2

    公开(公告)日：2015-07-14

    申请号：US13566710

    申请日：2012-08-03

    Applicant: Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    Inventor： Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    IPC: H01L21/336 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

    CPC classification number: H01L27/11521 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/42356 ,  H01L29/66833 ,  H01L29/792

    Abstract: The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

    Abstract translation: 本公开描述了形成存储器件的方法。 该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极， 以及在所述控制多晶堆叠图案中形成控制栅极。 形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。

    Method of Forming an Embedded Memory Device
    5.
    发明申请
    Method of Forming an Embedded Memory Device 有权
    形成嵌入式存储器件的方法

    公开(公告)号：US20140035020A1

    公开(公告)日：2014-02-06

    申请号：US13566710

    申请日：2012-08-03

    Applicant: Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    Inventor： Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    IPC: H01L29/788 ,  H01L21/336

    CPC classification number: H01L27/11521 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/42356 ,  H01L29/66833 ,  H01L29/792

    Abstract: The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

    Abstract translation: 本公开描述了形成存储器件的方法。 该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极， 以及在所述控制多晶堆叠图案中形成控制栅极。 形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。

    Embedded Transistor
    6.
    发明申请
    Embedded Transistor 有权

    公开(公告)号：US20130092989A1

    公开(公告)日：2013-04-18

    申请号：US13273012

    申请日：2011-10-13

    Applicant: Yu-Wei Ting ,  Kuo-Ching Huang

    Inventor： Yu-Wei Ting ,  Kuo-Ching Huang

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/66621 ,  H01L29/78

    Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell.

    System and Method for Coupling an Integrated Circuit to a Circuit Board
    7.
    发明申请
    System and Method for Coupling an Integrated Circuit to a Circuit Board 有权
    将集成电路耦合到电路板的系统和方法

    公开(公告)号：US20080318454A1

    公开(公告)日：2008-12-25

    申请号：US11766204

    申请日：2007-06-21

    Applicant: Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

    Inventor： Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

    IPC: H01R12/16

    CPC classification number: H05K1/0271 ,  H05K2201/044 ,  H05K2201/09063 ,  H05K2201/10409 ,  H05K2201/10734

    Abstract: An information handling system circuit board has an opening formed through it proximate a coupling point of an integrated circuit to the circuit board. The opening manages stress at the coupling point of the integrated circuit to the circuit board to reduce the risk of damage to the coupling point during deformation of the circuit board, such as when the circuit board is coupled to a chassis or when a component is pressed into the circuit board. In one embodiment, rectangular openings are formed at diagonally opposed corners of a BSA integrated circuit. In alternative embodiments, openings of varying shape, such as slots or curved slots, are formed at selected corners of the integrated circuit.

    Abstract translation: 信息处理系统电路板具有通过其形成的开口，其靠近集成电路到电路板的耦合点。 开口处理集成电路到电路板的耦合点处的应力，以减少在电路板变形期间对耦合点的损坏的风险，例如当电路板耦合到底盘或当部件被按压时 进入电路板。 在一个实施例中，在BSA集成电路的对角相对的角上形成矩形开口。 在替代实施例中，在集成电路的选定角处形成变化形状的开口，例如槽或弯曲槽。

    CLAMP FOR FIXING A PHOTOGRAPHIC SLIDE OR NEGATIVE
    8.
    发明申请
    CLAMP FOR FIXING A PHOTOGRAPHIC SLIDE OR NEGATIVE 审中-公开
    用于固定摄影幻灯片或负片的夹具

    公开(公告)号：US20060061837A1

    公开(公告)日：2006-03-23

    申请号：US10904740

    申请日：2004-11-24

    Applicant: Kuo-Ching Huang ,  Yu-Cheng Chang

    Inventor： Kuo-Ching Huang ,  Yu-Cheng Chang

    IPC: H04N1/23

    CPC classification number: H04N1/1013 ,  H04N2201/0406 ,  H04N2201/0408 ,  H04N2201/0422

    Abstract: A clamp for fixing a photographic slide and/or a photographic negative includes a carrier and a cover for fixing the slide or negative onto the carrier. The carrier includes a first guide for holding the negative, and a second guide extended from the first guide for holding the photographic slide.

    Abstract translation: 用于固定照相底片和/或照相底片的夹具包括用于将滑块或阴极固定到载体上的载体和盖。 载体包括用于保持负片的第一引导件和从第一引导件延伸以保持照相载玻片的第二引导件。

    Hand-held deivce
    9.
    发明授权
    Hand-held deivce 有权
    手持式活动

    公开(公告)号：US08825122B2

    公开(公告)日：2014-09-02

    申请号：US13239359

    申请日：2011-09-21

    Applicant: Che-Hung Huang ,  Kuo-Ching Huang ,  Chih-Ling Chien

    Inventor： Che-Hung Huang ,  Kuo-Ching Huang ,  Chih-Ling Chien

    IPC: H05K7/00 ,  G06F1/16 ,  H05K5/02 ,  H04M1/02

    CPC classification number: G06F1/1624 ,  H04M1/0237 ,  H04M1/0239

    Abstract: A hand-held device includes a first body, a second body, a sliding module, and a guiding module. The sliding module is disposed between the first body and the second body, so that the second body is able to be slid on a two-dimensional plane relative to the first body. The guiding module includes a first guiding part and a second guiding part. The first guiding part is fixed to the first body. The second guiding part is fixed to the second body and coupled to the first guiding part. Besides, the second guiding part is able to be moved along a guiding path relative to the first guiding part, so that the second body is able to be slid along the guiding path on the two-dimensional plane relative to the first body.

    Abstract translation: 手持式装置包括第一主体，第二主体，滑动模块和引导模块。 滑动模块设置在第一主体和第二主体之间，使得第二主体能够相对于第一主体在二维平面上滑动。 引导模块包括第一引导部分和第二引导部分。 第一个引导部分固定在第一个身体。 第二引导部分固定到第二主体并且联接到第一引导部分。 此外，第二引导部能够相对于第一引导部沿着引导路径移动，使得第二主体能够相对于第一主体沿着二维平面上的引导路径滑动。

    Structure for CMOS image sensor with a plurality of capacitors
    10.
    发明授权
    Structure for CMOS image sensor with a plurality of capacitors 有权
    具有多个电容器的CMOS图像传感器的结构

    公开(公告)号：US07847847B2

    公开(公告)日：2010-12-07

    申请号：US11044922

    申请日：2005-01-27

    Applicant: Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

    Inventor： Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

    IPC: H04N3/14 ,  H04N5/335

    CPC classification number: H04N5/361 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H04N5/3559 ,  H04N5/374 ,  H04N5/37452

    Abstract: A CMOS image sensor having increased capacitance that allows a photo-diode to generate a larger current is provided. The increased capacitance reduces noise and the dark signal. The image sensor utilizes a transistor having nitride spacers formed on a buffer oxide layer. Additional capacitance may be provided by various capacitor structures, such as a stacked capacitor, a planar capacitor, a trench capacitor, a MOS capacitor, a MIM/PIP capacitor, or the like. Embodiments of the present invention may be utilized in a 4-transistor pixel or a 3-transistor pixel configuration.

    Abstract translation: 提供了具有允许光电二极管产生较大电流的增加的电容的CMOS图像传感器。 增加的电容可以降低噪声和暗信号。 图像传感器利用形成在缓冲氧化物层上的具有氮化物间隔物的晶体管。 附加电容可以由诸如叠层电容器，平面电容器，沟槽电容器，MOS电容器，MIM / PIP电容器等的各种电容器结构来提供。 本发明的实施例可以用于4-晶体管像素或3-晶体管像素配置。

Patent Agency Ranking